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Estimation of Sample Clock Frequency Offset Using Error Vector Magnitude
KTH, School of Electrical Engineering (EES), Signal Processing.ORCID iD: 0000-0002-4265-9490
2011 (English)Patent (Other (popular science, discussion, etc.))
Abstract [en]

A low complexity system and method for operating a receiver in order to estimate an offset between the actual sample clock rate 1/TS' of a receiver and an intended sample clock rate 1/TS. The receiver captures samples of a received baseband signal at the rate 1/TS', operates on the captured samples to generate an estimate for the clock rate offset, and fractionally resamples the captured samples using the clock rate offset. The resampled data represents an estimate of baseband symbols transmitted by the transmitter. The action of operating on the captured samples involves computing an error vector signal and then estimating the clock rate offset using the error vector signal. The error vector signal may be computed in different ways depending on whether or not carrier frequency offset and carrier phase offset are assumed to be present in the received baseband signal.

Place, publisher, year, edition, pages
National Category
Electrical Engineering, Electronic Engineering, Information Engineering Signal Processing
URN: urn:nbn:se:kth:diva-120150OAI: diva2:613712
US 8442161-B2 (2013-05-14)

US8654903-B2 (2014-02-18)

Available from: 2013-04-01 Created: 2013-04-01 Last updated: 2015-04-09Bibliographically approved

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Yajnanarayana, Vijaya
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