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Creation and validation of flows with IEEE1500 test wrapper for core-based test methodology
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2012 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

System-on-Chips are getting more complex every day, making manufacturing test constantly more challenging. As chip size is increasing, a divide and conquer approach is tackled, through a core-based methodology, using Synopsys Design-for-Test (DfT) state of the art features. This document deals with flows implementing such architectures. A wrapping core flow is proposed, limiting ports impact, thanks to compression feature. A full automated flow is proposed, as well as one offering more test possibilities, implementing wrapper bypass paths for full custom tests.

Then a top-down flow is presented to tackle an actual complex ST-Ericsson project, using most of Synopsys features, showing first how to use the tool and which workarounds are to be implemented to achieve the expected architecture.

As a parallel study, clock management under test, which is one of the most challenging parts in DfT flows, was examined. Clocks are handled with On-Chip-Clocking (OCC) controller, setting dynamically clock behavior through clock chains. It was shown that all clock chains should be handled in a single scan chain through compression modules. As a consequence, and to avoid a longer clock chain than regular chains, an update of the current Synopsys OCC controller was proposed, improving test time in coming projects.

Abstract [sv]

System-on-Chip blir mer och mer komplexa, och det komplicerar chips tillverkningenstestar. På grund av chip storleks ökning, presenteras en ”divide-and-conquer” teknik med en ”core-based” metod och Synopsyss Design-for-Test (DfT) toppmoderna funktioner. Det här dokumentet utveklar flöder med sådana arkitekturer. Först föreslås ett wrapper IP flöden, som användar kompressions flöd för att begränsa påverkan om pads. Sedan en ”top-down” flöd presenteras för att hantera en verklig komplex ST-Ericssons projekt, med många Synopsyss funktioner. Verktygs begränsningar först visas, sedan sätter att komma runt dem presenteras för att få förvantade arkitekturen.

En andra studie är klocka förvaltning under test kontrolleras med så kallade ”On-Chip-Clocking (OCC) controller”. Den här funktionen undersöks och studien bevisar att alla OCC kontroll bitarna bör hanteras i en enda clock-chain genom kompression moduler. Som en följd av det och för att undvika en längre clock-chain än vanliga scan chains, är här en OCC kontrollers uppdatering föreslås, minskar testtid i kommande projekt.

Place, publisher, year, edition, pages
2012. , 63 p.
Trita-ICT-EX, 2012:272
National Category
Engineering and Technology
URN: urn:nbn:se:kth:diva-121291OAI: diva2:618065
Available from: 2013-04-25 Created: 2013-04-25 Last updated: 2013-04-25Bibliographically approved

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