Automatic test program generation framework for NoC-based MPSoC compiler validation
2011 (English)In: 2011 International Conference on Instrumentation, Measurement, Circuits and Systems (ICIMCS 2011), vol 1: Instrumentation, Measurement, Circuits and Systems, New York: Amer Soc Mechanical Engineers , 2011, 99-103 p.Conference paper (Refereed)
In this paper, we propose a systematic method (a framework) for automatic test program generation for Network-on-Chip (NoC) based Multi-Processor System-on-Chip (MPSoC) compiler validation. This framework consists of three parts: specification reader, program generator and platform simulator. By applying this framework, specified test programs for compiler validation are automatically generated as well as their corresponding run time results. The validation productivity is enhanced and the expertise requirement is reduced. We also present an example tool called Automatic VESYLA Generator (AVG) implementing this framework. This tool is used in the Dynamic Reconfigurable Resource Array (DRRA) assembler development in our research group. The experiment shows that on a personal PC, AVG tool generates bug-free test programs more than 100 times faster than a human programmer.
Place, publisher, year, edition, pages
New York: Amer Soc Mechanical Engineers , 2011. 99-103 p.
Network-on-Chip, Automatic Test Program Generation, Compiler Validation, DRRA
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-121363DOI: 10.1115/1.859902.paper21ISI: 000306295500021ISBN: 978-0-7918-5990-2OAI: oai:DiVA.org:kth-121363DiVA: diva2:618685
International Conference on Instrumentation, Measurement, Circuits and Systems (ICIMCS 2011)
QC 201304292013-04-292013-04-292013-07-04Bibliographically approved