The RecoBlock SoC Platform: A Flexible Array of Reusable Run-Time-Reconfigurable IP-Blocks
2013 (English)In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013, 833-838 p.Conference paper (Refereed)
Run-time reconfigurable (RTR) FPGAs combine the flexibility of software with the high efficiency of hardware. Still, their potential cannot be fully exploited due to increased complexity of the design process. Consequently, to enable an efficient design flow, we devise a set of prerequisites to increase the flexibility and reusability of current FPGA-based RTR architectures. We apply these principles to design and implement the RecoBlock SoC platform, which main characterization is (1) a RTR plug-and-play IP-Core whose functionality is configured at run-time; (2) flexible inter-block communication configured via software, and (3) built-in buffers to support data-driven streams and inter-process communications. We illustrate the potential of our platform by a tutorial case study using an adaptive streaming application to investigate different combinations of reconfigurable arrays and schedules. The experiments underline the benefits of the platform and shows resource utilization.
Place, publisher, year, edition, pages
2013. 833-838 p.
, Design, Automation, and Test in Europe Conference and Exhibition. Proceedings, ISSN 1530-1591
reconfigurable architectures, partial and run-time reconfiguration, system-on-chip, adaptivity, embedded systems
Embedded Systems Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-121778DOI: 10.7873/DATE.2013.176ScopusID: 2-s2.0-84885655414ISBN: 978-1-4673-5071-6OAI: oai:DiVA.org:kth-121778DiVA: diva2:619553
Design, Automation & Test in Europe (DATE'13); Grenoble, France, 18-22 March 2013
QC 201308222013-05-042013-05-042015-12-01Bibliographically approved