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Design Space Exploration of Clock-pumping Techniques to Reduce Through-Silicon-Via (TSV) Manufacturing Cost In 3-D Integration
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2012 (English)In: Proceedings of the 2012 IEEE 14th Electronics Packaging Technology Conference, EPTC 2012, IEEE , 2012, 19-22 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we explore the cost of clock pumping techniques implemented for scalable 3-D Integrated Systems in the complexity of interconnect, circuit, and architecture level changes. Their effect in terms of area and power for comparable performance is estimated. Our results show that by using 50% of the number of TSVs, we achieve the same performance as standard implementation with insignificant area and power overhead from the overall system cost. The proposed pumping technique can be used as one of the components in 3-D systems design for several applications that require logic-on-logic or memory-on-logic stacking.

Place, publisher, year, edition, pages
IEEE , 2012. 19-22 p.
Keyword [en]
3D networks, Communication architectures, Communication schemes, Communication topologies, Cycle accurate, Design constraints, Design guidelines, Global interconnect delay, Integrated electronics, Network on chip, Technology solutions, Through silicon vias, Traffic pattern, Biological materials, Electric network topology, Interconnection networks, Microprocessor chips, Network performance, Routers, Scalability, Systems engineering, Three dimensional
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-122297DOI: 10.1109/EPTC.2012.6507043ISI: 000320276500005Scopus ID: 2-s2.0-84879751133ISBN: 978-1-4673-4553-8 (print)OAI: oai:DiVA.org:kth-122297DiVA: diva2:621913
Conference
2012 IEEE 14th Electronics Packaging Technology Conference, EPTC 2012; Singapore; Singapore; 5 December 2012 through 7 December 2012
Note

QC 20130528

Available from: 2013-05-17 Created: 2013-05-17 Last updated: 2015-12-21Bibliographically approved
In thesis
1. Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture
Open this publication in new window or tab >>Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Three-Dimensional (3D) integration of circuits based on die and wafer stacking using through-silicon-via is a critical technology in enabling "more-than-Moore", i.e. functional integration of devices beyond pure scaling ("more Moore"). In particular, the scaling from multi-core to many-core architecture is an excellent candidate for such integration. 3D systems design follows is a challenging and a complex design process involving integration of heterogeneous technologies. It is also expensive to prototype because the 3D industrial ecosystem is not yet complete and ready for low-cost mass production. Networks-on-Chip (NoCs) efficiently facilitates the communication of massively integrated cores on 3D many-core architecture. In this thesis scalability and performance issues of NoCs are explored in terms of architecture, organization and functionality of many-core systems.

First, we evaluate on-chip network performance in massively integrated many-core architecture when network size grows. We propose link and channel models to analyze the network traffic and hence the performance. We develop a NoC simulation framework to evaluate the performance of a deflection routing network as the architecture scales up to 1000 cores. We propose and perform comparative analysis of 3D processor-memory model configurations in scalable many-core architectures.

Second, we investigate how the deflection routing NoCs can be designed to maximize the benefit of the fast TSVs through clock pumping techniques. We propose multi-rate models for inter-layer communication. We quantify the performance benefit through cycle-accurate simulations for various configurations of 3D architectures.

Finally, the complexity of massively integrated many-core architecture by itself brings a multitude of design challenges such as high-cost of prototyping, increasing complexity of the technology, irregularity of the communication network, and lack of reliable simulation models. We formulate a zero-load average distance model that accurately predicts the performance of deflection routing networks in the absence of data flow by capturing the average distance of a packet with spatial and temporal probability distributions of traffic.

The thesis research goals are to explore the design space of vertical integration for many-core applications, and to provide solutions to 3D technology challenges through architectural innovations. We believe the research findings presented in the thesis work contribute in addressing few of the many challenges to the field of combined research in many-core architectural design and 3D integration technology.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2016. xviii, 80 p.
Series
TRITA-ICT, 2015:29
Keyword
Alpha-model, Average distance, B-Model, NoC, Zero-load predictive model, deflection routing, q-routing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-179694 (URN)978-91-7595-803-3 (ISBN)
Public defence
2016-01-20, Hall C, Electrum, Isafjordsgatan 26, 16440, Kista, 13:00 (English)
Opponent
Supervisors
Note

QC 20151221

Available from: 2015-12-21 Created: 2015-12-21 Last updated: 2015-12-21Bibliographically approved

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