Design Space Exploration of Clock-pumping Techniques to Reduce Through-Silicon-Via (TSV) Manufacturing Cost In 3-D Integration
2012 (English)In: Proceedings of the 2012 IEEE 14th Electronics Packaging Technology Conference, EPTC 2012, IEEE , 2012, 19-22 p.Conference paper (Refereed)
In this paper, we explore the cost of clock pumping techniques implemented for scalable 3-D Integrated Systems in the complexity of interconnect, circuit, and architecture level changes. Their effect in terms of area and power for comparable performance is estimated. Our results show that by using 50% of the number of TSVs, we achieve the same performance as standard implementation with insignificant area and power overhead from the overall system cost. The proposed pumping technique can be used as one of the components in 3-D systems design for several applications that require logic-on-logic or memory-on-logic stacking.
Place, publisher, year, edition, pages
IEEE , 2012. 19-22 p.
3D networks, Communication architectures, Communication schemes, Communication topologies, Cycle accurate, Design constraints, Design guidelines, Global interconnect delay, Integrated electronics, Network on chip, Technology solutions, Through silicon vias, Traffic pattern, Biological materials, Electric network topology, Interconnection networks, Microprocessor chips, Network performance, Routers, Scalability, Systems engineering, Three dimensional
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-122297DOI: 10.1109/EPTC.2012.6507043ISI: 000320276500005ScopusID: 2-s2.0-84879751133ISBN: 978-1-4673-4553-8OAI: oai:DiVA.org:kth-122297DiVA: diva2:621913
2012 IEEE 14th Electronics Packaging Technology Conference, EPTC 2012; Singapore; Singapore; 5 December 2012 through 7 December 2012
QC 201305282013-05-172013-05-172015-12-21Bibliographically approved