A manufacturable process integration approach for graphene devices
2013 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 84, 185-190 p.Article in journal (Refereed) Published
In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.
Place, publisher, year, edition, pages
2013. Vol. 84, 185-190 p.
Graphene, Transistors, Process integration, Hot electrons, Quantum capacitance, Dielectric breakdown
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-124456DOI: 10.1016/j.sse.2013.02.008ISI: 000319547100026ScopusID: 2-s2.0-84879505639OAI: oai:DiVA.org:kth-124456DiVA: diva2:636307
42nd European Solid-State Device Research Conference (ESSDERC), SEP, 2012, Bordeaux, FRANCE
QC 201307092013-07-092013-07-052016-05-03Bibliographically approved