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Wafer-level 3-D CMOS Integration of Very-large-scale Silicon Micromirror Arrays and Room-temperature Wafer-level Packaging
KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
2013 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

This thesis describes the development of wafer-level fabrication and packaging methods for micro-electromechanical (MEMS) devices, based on wafer-bonding.

The first part of the thesis is addressing the development of a wafer-level technology that allows the use of high performance materials, such as monocrystalline silicon, for MEMS devices that are closely integrated on top of sensitive integrated circuits substrates. Monocrystalline silicon has excellent mechanical properties that are hard to achieve otherwise, and therefore it fits well in devices for adaptive optics and maskwriting applications where nanometer precision deflection requirements call for mechanically stable materials. However, the temperature sensitivity of the integrated circuits prohibits the use of monocrystalline silicon with conventional deposition and surface micromachining techniques. Here, heterogeneous 3-D integration by adhesive wafer-bonding is used to fabricate three different types of spatial light modulators, based on micromirror arrays made of monocrystalline silicon; micromirror arrays with vertically moving “piston-type” mirrors and with tilting mirrors made of one functional monocrystalline silicon layer, and vertically moving hidden-hinge micromirror arrays made of two functional monocrystalline silicon layers.

The second part of the thesis addresses the need for room-temperature packaging methods that allow the packaging of liquids or in general heat sensitive devices on wafer-level. A packaging method was developed that is based on a hybrid wafer-bonding approach, combining the compression bonding of gold gaskets with adhesive bonding. The packaging method is first demonstrated for the wafer-level encapsulation of liquids in reservoirs and then applied to packaging a dye-based photonic gas sensor.

 

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2013. , xi, 126 p.
Series
Trita-EES, 2013:031
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-125913ISBN: 978-91-7501-843-0 (print)OAI: oai:DiVA.org:kth-125913DiVA: diva2:641378
Public defence
2013-09-06, F3, Lindstedtsvägen 26, KTH, Stockholm, 14:14 (English)
Opponent
Supervisors
Note

QC 20130816

Available from: 2013-08-16 Created: 2013-08-16 Last updated: 2013-08-19Bibliographically approved
List of papers
1. Wafer bonding with nano-imprint resists as sacrificial adhesive for fabrication of silicon-on-integrated-circuit (SOIC) wafers in 3D integration of MEMS and ICs
Open this publication in new window or tab >>Wafer bonding with nano-imprint resists as sacrificial adhesive for fabrication of silicon-on-integrated-circuit (SOIC) wafers in 3D integration of MEMS and ICs
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2009 (English)In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 154, no 1, 180-186 p.Article in journal (Refereed) Published
Abstract [en]

In this paper, we present the use of thermosetting nano-imprint resists in adhesive wafer bonding. The presented wafer bonding process is suitable for heterogeneous three-dimensional (3D) integration of microelectromechanical systems (MEMS) and integrated circuits (ICs). Detailed adhesive bonding process parameters are presented to achieve void-free, well-defined and uniform wafer bonding interfaces. Experiments have been performed to optimize the thickness control and uniformity of the nano-imprint resist layer in between the bonded wafers. In contrast to established polymer adhesives such as, e.g., BCB, nano-imprint resists as adhesives for wafer-to-wafer bonding are specifically suitable if the adhesive is intended as sacrificial material. This is often the case, e.g., in fabrication of silicon-on-integrated-circuit (SOIC) wafers for 3D integration of MEMS membrane structures on top of IC wafers. Such IC integrated MEMS includes. e.g., micro-mirror arrays, infrared bolometer arrays, resonators, capacitive inertial sensors, pressure sensors and microphones.

Keyword
Adhesive wafer bonding, Nano-imprint resist, Polymer, 3D IC MEMS, integration, Silicon-on-integrated-circuit, SOIC, nanoimprint lithography, polymer deformation, arrays, thermosets, design, flow
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-18753 (URN)10.1016/j.sna.2009.07.009 (DOI)000269771200028 ()2-s2.0-68849118449 (Scopus ID)
Note
QC 20100525Available from: 2010-08-05 Created: 2010-08-05 Last updated: 2017-12-12Bibliographically approved
2. Drift-free micromirror arrays made of monocrystalline silicon for adaptive optics applications
Open this publication in new window or tab >>Drift-free micromirror arrays made of monocrystalline silicon for adaptive optics applications
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2012 (English)In: Journal of microelectromechanical systems, ISSN 1057-7157, E-ISSN 1941-0158, Vol. 21, no 4, 959-970 p.Article in journal (Refereed) Published
Abstract [en]

In this paper, we report on the heterogeneous integration of monocrystalline silicon membranes for the fabrication of large segmented micromirror arrays for adaptive optics applications. The design relies on a one-level architecture with mirrors and suspension formed within the same material, employing a large actuator gap height of up to 5.1 μ m to allow for a piston-type mirror deflection of up to 1600 nm. Choosing monocrystalline silicon as actuator and mirror material, we demonstrate a completely drift-free operation capability. Furthermore, we investigate stress effects that degrade the mirror topography, and we show that the stress originates from the donor silicon-on-insulator wafer. The novel heterogeneous integration strategy used in this work is capable of reducing this stress to a large extent.

Keyword
Heterogeneous integration, mirrors, silicon, spatial light modulators (SLMs), very large scale integration, wafer bonding, wafer-scale integration
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-99161 (URN)10.1109/JMEMS.2012.2190713 (DOI)000307124200026 ()2-s2.0-84864579675 (Scopus ID)
Funder
EU, European Research Council
Note

QC 20120830

Available from: 2012-07-15 Created: 2012-07-15 Last updated: 2017-12-07Bibliographically approved
3. One-Megapixel Monocrystalline-Silicon Micromirror Array on CMOS Driving Electronics Manufactured With Very Large-Scale Heterogeneous Integration
Open this publication in new window or tab >>One-Megapixel Monocrystalline-Silicon Micromirror Array on CMOS Driving Electronics Manufactured With Very Large-Scale Heterogeneous Integration
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2011 (English)In: Journal of microelectromechanical systems, ISSN 1057-7157, E-ISSN 1941-0158, Vol. 20, no 3, 564-572 p.Article in journal (Refereed) Published
Abstract [en]

In this paper, we demonstrate the first high-resolution spatial-light-modulator chip with 1 million tilting micromirrors made of monocrystalline silicon on analog high-voltage complementary metal-oxide-semiconductor driving electronics. This device, as result of a feasibility study, shows good optical and excellent mechanical properties. The micromirrors exhibit excellent surface properties, with a surface roughness below 1-nm root mean square. Actuated micromirrors show no imprinting behavior and operate drift free. Very large-scale heterogeneous integration was used to fabricate the micromirror arrays. The detailed fabrication process is presented in this paper, together with a characterization of the SLM devices. Large arrays of individually controllable micromirrors are the enabling component in high-perfomance mask-writing systems and promising for high throughput deep-ultraviolet maskless lithography systems. The adoption of new materials with enhanced characteristics is critical in meeting the challenging demands with regard to surface quality and operation stability in the future. Very large-scale heterogeneous integration may enable virtually any solid-state material to be integrated together with CMOS electronics. [2010-0272]

Keyword
Complementary metal-oxide-semiconductor (CMOS) integrated circuits, heterogeneous integration, mirrors, photolithography, silicon, spatial light modulators (SLMs), very large-scale integration, wafer bonding, wafer-scale integration
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-35131 (URN)10.1109/JMEMS.2011.2127454 (DOI)000291316000006 ()2-s2.0-79957993226 (Scopus ID)
Note
QC 20110623Available from: 2011-06-23 Created: 2011-06-20 Last updated: 2017-12-11Bibliographically approved
4. Heterogeneous 3D integration of hidden hinge micromirror arrays consisting of two layers of monocrystalline silicon
Open this publication in new window or tab >>Heterogeneous 3D integration of hidden hinge micromirror arrays consisting of two layers of monocrystalline silicon
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2013 (English)In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 23, no 7, 075003- p.Article in journal (Refereed) Published
Abstract [en]

We present a complementary metal–oxide–semiconductor (CMOS) compatible heterogeneous 3D integration process that allows the integration of two monocrystalline silicon layers on top of CMOS control electronics. With this process we demonstrate the fabrication of hidden hinge micromirror arrays from monocrystalline silicon for adaptive optics applications. The piston-type micromirror arrays have the flexures underneath the mirror plates on separate silicon layers. Arrays of 48 × 48 mirror elements with an air-gap between mirror and address electrode of 10 µm were fabricated. The mirrors were found to be drift free and showed no imprinting. A maximum electrostatic mirror displacement of 3 µm is demonstrated.

Keyword
heterogeneous integration, spatial light modulators, micromirror arrays, monocrystalline silicon, CMOS compatible, hidden-hinge mirrors, adaptive optics
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-124539 (URN)10.1088/0960-1317/23/7/075003 (DOI)000321063300012 ()2-s2.0-84879739892 (Scopus ID)
Projects
q2m
Note

QC 20130709

Available from: 2013-07-09 Created: 2013-07-09 Last updated: 2017-12-06Bibliographically approved
5. Wafer-Level capping and sealing of heat sensitive substances and liquids with gold gaskets
Open this publication in new window or tab >>Wafer-Level capping and sealing of heat sensitive substances and liquids with gold gaskets
Show others...
2013 (English)In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 201, 154-163 p.Article in journal (Refereed) Published
Abstract [en]

This paper reports on a novel wafer-level packaging method employing gold gaskets and an epoxy underfill. The packaging is done at room-temperature and atmospheric pressure. The mild packaging conditions allow the encapsulation of sensitive devices. The method is demonstrated for two applications; the wafer-level encapsulation of a liquid and the wafer-level packaging of a photonic gas sensor containing heat sensitive dye-films.

Place, publisher, year, edition, pages
Elsevier, 2013
Keyword
Wafer-level packaging, Liquid sealing, Room-temperature, Underfill application, Gasket
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-119838 (URN)10.1016/j.sna.2013.07.007 (DOI)000325836400020 ()2-s2.0-84881511190 (Scopus ID)
Projects
Phodye
Funder
EU, European Research Council
Note

QC 20131129

Available from: 2013-03-24 Created: 2013-03-24 Last updated: 2017-12-06Bibliographically approved
6. A wafer-scale, dye-based, photonic sensing system
Open this publication in new window or tab >>A wafer-scale, dye-based, photonic sensing system
Show others...
(English)Manuscript (preprint) (Other academic)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-126087 (URN)
Note

QS 2013

Available from: 2013-08-19 Created: 2013-08-19 Last updated: 2013-08-19Bibliographically approved

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