Adding DRAM and SRAM support for the NoC Generator
Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
A NoC generator tool that generate an arbitrarily large Multi-core platform, targeted for single-chip FPGA platforms was developed in 2011 by Johnny Öberg and Francesco Robino in the department of electronic system, KTH, Sweden. In the current implementation of the platform, only on-chip memory is supported. However, the size of the data the system needs to handle is often too large to fit in those memories. Thus, external memory access to both SRAM and SDRAM on the FPGA board is needed. Adding external memories to an FPGA system takes a lot of time and hard studies in the Altera platform handbooks. Adding this feature to the NoC generator would save a lot of time for the platform developers
In this thesis, an example design using external memories is analysed to obtain the necessary information needed to update the NoC generator to support SRAM and SDRAM.
Place, publisher, year, edition, pages
2013. , 35 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-128725OAI: oai:DiVA.org:kth-128725DiVA: diva2:648528
Master of Science in Engineering - Microelectronics
Sandqvist, William, Lecturer