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Energy-Aware Coarse-Grained Reconfigurable Architectures using Dynamically Reconfigurable Isolation Cells
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
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2013 (English)In: Proceedings Of The Fourteenth International Symposium On Quality Electronic Design (ISQED 2013), 2013, 104-111 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a self adaptive architecture to enhance the energy efficiency of coarse-grained reconfigurable architectures (CGRAs). Today, platforms host multiple applications, with arbitrary inter-application communication and concurrency patterns. Each application itself can have multiple versions (implementations with different degree of parallelism) and the optimal version can only be determined at runtime. For such scenarios, traditional worst case designs and compile time mapping decisions are neither optimal nor desirable. Existing solutions to this problem employ costly dedicated hardware to configure the operating point at runtime (using DVFS). As an alternative to dedicated hardware, we propose exploiting the reconfiguration features of modern CGRAs. Our solution relies on dynamically reconfigurable isolation cells (DRICs) and autonomous parallelism, voltage, and frequency selection algorithm (APVFS). The DRICs reduce the overheads of DVFS circuitry by configuring the existing resources as isolation cells. APVFS ensures high efficiency by dynamically selecting the parallelism, voltage and frequency trio, which consumes minimum power to meet the deadlines on available resources. Simulation results using representative applications (Matrix multiplication, FIR, and FFT) showed up to 23% and 51% reduction in power and energy, respectively, compared to traditional DVFS designs. Synthesis results have confirmed significant reduction in area overheads compared to state of the art DVFS methods.

Place, publisher, year, edition, pages
2013. 104-111 p.
Series
International Symposium on Quality Electronic Design, ISSN 1948-3295
Keyword [en]
Adaptive architecture, Coarse grained reconfigurable architecture, Dedicated hardware, Degree of parallelism, Frequency selection, Inter-application communications, MAtrix multiplication, Multiple applications
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-132219DOI: 10.1109/ISQED.2013.6523597ISI: 000324653700016Scopus ID: 2-s2.0-84879575023ISBN: 978-1-4673-4952-9 (print)OAI: oai:DiVA.org:kth-132219DiVA: diva2:659114
Conference
14th International Symposium on Quality Electronic Design, ISQED 2013; Santa Clara, CA; United States; 4 March 2013 through 6 March 2013
Note

QC 20131024

Available from: 2013-10-24 Created: 2013-10-24 Last updated: 2013-10-24Bibliographically approved

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Hemani, Ahmed

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