Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains
2014 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, Vol. 22, no 3, 641-654 p.Article in journal (Refereed) Published
In this paper, we introduce a source-synchronous adaptive interface for the globally ratiochronous, locally synchronous design style, a subset of the globally asynchronous, locally synchronous (GALS) design style in which the frequencies of all clocks are not phase-aligned but are constrained to be rationally related, i.e., they are all submultiple of the same physical or virtual frequency. The interface can be designed using only standard cells and guarantees maximal throughput in addition to an average latency four times lower compared with state-of-the-art asynchronous first-input, first-output GALS interfaces. Several properties of the interface are formally stated and proved. We also demonstrate that the interface has a low area overhead, with only four flip-flops per data line, and is robust against nonidealities such as clock jitters and propagation delay misalignments. For a realistic link in 90-nm application-specific integrated circuit technology, we derive a 1-GHz upper bound for the least common multiple among the frequencies.
Place, publisher, year, edition, pages
2014. Vol. 22, no 3, 641-654 p.
Application specific integrated circuits, asynchronous circuits, circuits, circuits and systems, system-on-a-chip
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-132264DOI: 10.1109/TVLSI.2013.2252030ISI: 000332124200018ScopusID: 2-s2.0-84896769941OAI: oai:DiVA.org:kth-132264DiVA: diva2:659397
QC 201403172013-10-252013-10-252014-04-07Bibliographically approved