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39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0002-4157-4487
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
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2013 (English)In: 2013 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE , 2013, 1448-1451 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents an industrial case study of using a Coarse Grain Reconfigurable Architecture (CGRA) for a multi-mode accelerator for two kernels: FFT for the LTE standard and the Correlation Pool for the UMTS standard to be executed in a mutually exclusive manner. The CGRA multi-mode accelerator achieved computational efficiency of 39.94 GOPS/watt (OP is multiply-add) and silicon efficiency of 56.20 GOPS/mm2. By analyzing the code and inferring the unused features of the fully programmable solution, an in-house developed tool was used to automatically customize the design to run just the two kernels and the two efficiency metrics improved to 49.05 GOPS/watt and 107.57 GOPS/mm2. Corresponding numbers for the ASIC implementation are 63.84 GOPS/watt and 90.91 GOPS/mm2. Though the ASIC’s silicon and computational efficiency numbers are slightly better, the engineering efficiency of the pre-verified/characterized CGRA solution is at least 10X better than the ASIC solution.

Place, publisher, year, edition, pages
IEEE , 2013. 1448-1451 p.
Series
IEEE International Symposium on Circuits and Systems, ISSN 0271-4310
Keyword [en]
Coarse-grain reconfigurable architectures, Efficiency metrics, Engineering efficiency, Fully programmables, Industrial case study, Multi-standard, Silicon efficiency, UMTS standard
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering Telecommunications Signal Processing
Identifiers
URN: urn:nbn:se:kth:diva-132265DOI: 10.1109/ISCAS.2013.6572129ISI: 000332006801171Scopus ID: 2-s2.0-84883388914ISBN: 9781467357609 (print)OAI: oai:DiVA.org:kth-132265DiVA: diva2:659403
Conference
2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013; Beijing; China; 19 May 2013 through 23 May 2013
Note

QC 20131104

Available from: 2013-10-25 Created: 2013-10-25 Last updated: 2017-03-27Bibliographically approved
In thesis
1. SiLago: Enabling System Level Automation Methodology to Design Custom High-Performance Computing Platforms: Toward Next Generation Hardware Synthesis Methodologies
Open this publication in new window or tab >>SiLago: Enabling System Level Automation Methodology to Design Custom High-Performance Computing Platforms: Toward Next Generation Hardware Synthesis Methodologies
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Place, publisher, year, edition, pages
Stockholm, Sweden: KTH Royal Institute of Technology, 2016. 56 p.
Series
TRITA-ICT, 2016:05
Keyword
System Level Synthesis, High Level Synthesis, VLSI Design Methodology, Brain-like Computation, Neuromorphic Hardware, Address Generation, Thread Level Parallelism
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-185787 (URN)978-91-7595-900-9 (ISBN)
Public defence
2016-05-17, Sal B, Electrum 229, Isafjordsgatan 22, Kista, Stockholm, 20:24 (English)
Opponent
Supervisors
Note

QC 20160428

Available from: 2016-04-28 Created: 2016-04-27 Last updated: 2016-04-28Bibliographically approved

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Li, ShuoHemani, Ahmed

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