39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation
2013 (English)In: 2013 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE , 2013, 1448-1451 p.Conference paper (Refereed)
This paper presents an industrial case study of using a Coarse Grain Reconfigurable Architecture (CGRA) for a multi-mode accelerator for two kernels: FFT for the LTE standard and the Correlation Pool for the UMTS standard to be executed in a mutually exclusive manner. The CGRA multi-mode accelerator achieved computational efficiency of 39.94 GOPS/watt (OP is multiply-add) and silicon efficiency of 56.20 GOPS/mm2. By analyzing the code and inferring the unused features of the fully programmable solution, an in-house developed tool was used to automatically customize the design to run just the two kernels and the two efficiency metrics improved to 49.05 GOPS/watt and 107.57 GOPS/mm2. Corresponding numbers for the ASIC implementation are 63.84 GOPS/watt and 90.91 GOPS/mm2. Though the ASIC’s silicon and computational efficiency numbers are slightly better, the engineering efficiency of the pre-verified/characterized CGRA solution is at least 10X better than the ASIC solution.
Place, publisher, year, edition, pages
IEEE , 2013. 1448-1451 p.
, IEEE International Symposium on Circuits and Systems, ISSN 02714310
Coarse-grain reconfigurable architectures, Efficiency metrics, Engineering efficiency, Fully programmables, Industrial case study, Multi-standard, Silicon efficiency, UMTS standard
Other Electrical Engineering, Electronic Engineering, Information Engineering Telecommunications Signal Processing
IdentifiersURN: urn:nbn:se:kth:diva-132265DOI: 10.1109/ISCAS.2013.6572129ISI: 000332006801171ScopusID: 2-s2.0-84883388914ISBN: 978-146735760-9OAI: oai:DiVA.org:kth-132265DiVA: diva2:659403
2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013; Beijing; China; 19 May 2013 through 23 May 2013
QC 201311042013-10-252013-10-252016-04-28Bibliographically approved