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A conceptual custom super-computer design for real-time simulation of human brain
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
2013 (English)In: 2013 21st Iranian Conference on Electrical Engineering, ICEE 2013, 2013, 1-6 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we introduce BRIC, a novel custom multi-chip digital computer architecture for simulating in realtime a model of human brain in form of a spiking Bayesian Confidence Propagation Neural Network (BCPNN). The design is conceptually dimensioned for available technology in 2015-2020 with the estimated size of a pizza box, consuming less than 3 kWs of power, delivering 800 Teraflops/sec (single precision multiply operation) and 30 TBs of memory. To the best of our knowledge, this will be the smallest and lowest power real-time brain simulation engine if manufactured. The silicon and computational efficiencies come from use of 3D memory stacking, innovation in algorithm and architectural customization. The chip will be programmable allowing experimentation with variants of the BCPNN brain model.

Place, publisher, year, edition, pages
2013. 1-6 p.
Series
Iranian Conference on Electrical Engineering, ISSN 2164-7054
Keyword [en]
belief networks, bioelectric phenomena, biology computing, brain models, digital simulation, neural nets, parallel architectures, parallel machines, real-time systems, 3D memory stacking, BCPNN brain model, BRIC, architectural customization, computational efficiencies, conceptual custom super-computer design, human brain model, multichip digital computer architecture, real-time brain simulation engine, real-time simulation, spiking Bayesian confidence propagation neural network, Bandwidth, Brain modeling, Computational modeling, Fabrics, Memory management, Neurons, Random access memory
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-132288DOI: 10.1109/IranianCEE.2013.6599755ISI: 000333194300234Scopus ID: 2-s2.0-84886879786ISBN: 978-1-4673-5634-3 (print)OAI: oai:DiVA.org:kth-132288DiVA: diva2:659461
Conference
2013 21st Iranian Conference on Electrical Engineering, ICEE 2013; Mashhad; Iran; 14 May 2013 through 16 May 2013
Note

QC 20140122

Available from: 2013-10-25 Created: 2013-10-25 Last updated: 2016-04-28Bibliographically approved
In thesis
1. SiLago: Enabling System Level Automation Methodology to Design Custom High-Performance Computing Platforms: Toward Next Generation Hardware Synthesis Methodologies
Open this publication in new window or tab >>SiLago: Enabling System Level Automation Methodology to Design Custom High-Performance Computing Platforms: Toward Next Generation Hardware Synthesis Methodologies
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Place, publisher, year, edition, pages
Stockholm, Sweden: KTH Royal Institute of Technology, 2016. 56 p.
Series
TRITA-ICT, 2016:05
Keyword
System Level Synthesis, High Level Synthesis, VLSI Design Methodology, Brain-like Computation, Neuromorphic Hardware, Address Generation, Thread Level Parallelism
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-185787 (URN)978-91-7595-900-9 (ISBN)
Public defence
2016-05-17, Sal B, Electrum 229, Isafjordsgatan 22, Kista, Stockholm, 20:24 (English)
Opponent
Supervisors
Note

QC 20160428

Available from: 2016-04-28 Created: 2016-04-27 Last updated: 2016-04-28Bibliographically approved

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Hemani, Ahmed

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