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Private configuration environments (PCE) for efficient reconfiguration, in CGRAs
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. University of Turku, Finland. (Turku Centre for Computer Science, Finland)
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
University of Turku, Finland. (Turku Centre for Computer Science, Finland)
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2013 (English)In: Proceedings Of The 2013 IEEE 24th International Conference On Application-Specific Systems, Architectures And Processors (ASAP 13), IEEE Computer Society, 2013, 227-236 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we propose a polymorphic configuration architecture, that can be tailored to efficiently support reconfiguration needs of the applications at runtime. Today, CGRAs host multiple applications, running simultaneously on a single platform. Novel CGRAs allow each application to exploit late binding and time sharing for enhancing the power and area efficiency. These features require frequent reconfigurations, making reconfiguration time a bottleneck for time critical applications. Existing solutions to this problem either employ powerful configuration architectures or hide configuration latency (using configuration caching). However, both these methods incur significant costs when designed for worst-case reconfiguration needs. As an alternative to worst-case dedicated configuration mechanism, we exploit reconfiguration to provide each application its private configuration environment (PCE). PCE relies on a morphable configuration infrastructure, a distributed memory sub-system, and a set of PCE controllers. The PCE controllers customize the morphable configuration infrastructure and reserve portion of the a distributed memory sub-system, to act as a context memory for each application, separately. Thereby, each application enjoys its own configuration environment which is optimal in terms of configuration speed, memory requirements and energy. Simulation results using representative applications (WLAN and Matrix Multiplication) showed that PCE offers up to 58 % reduction in memory requirements, compared to dedicated, worst case configuration architecture. Synthesis results show that the morphable reconfiguration architecture incurs negligible overheads (3 % area and 4 % power compared of a single processing element).

Place, publisher, year, edition, pages
IEEE Computer Society, 2013. 227-236 p.
Series
International Conference on Application-Specific Systems, Architecture and Processors. Proceedings, ISSN 1063-6862
Keyword [en]
Configuration mechanisms, Distributed Memory, MAtrix multiplication, Memory requirements, Multiple applications, Processing elements, Reconfiguration time, Time-critical applications
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-132289DOI: 10.1109/ASAP.2013.6567579ISI: 000328695600037Scopus ID: 2-s2.0-84883421912ISBN: 978-147990492-1 (print)OAI: oai:DiVA.org:kth-132289DiVA: diva2:659470
Conference
2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2013; Washington, DC; United States; 5 June 2013 through 7 June 2013
Note

QC 20131104

Available from: 2013-10-25 Created: 2013-10-25 Last updated: 2014-01-17Bibliographically approved

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Hemani, Ahmed

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Tajammul, Muhammad AdeelJafri, Syed Mohammad Asad HassanHemani, AhmedTenhunen, Hannu
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