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Energy-Aware-Task-Parallelism for Efficient Dynamic Voltage, and Frequency Scaling, in CGRAs
KTH, School of Information and Communication Technology (ICT), Electronic Systems. University of Turku, Finland.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
KTH, School of Information and Communication Technology (ICT), Electronic Systems. Indian Institute of Technology.
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2013 (English)In: Proceedings - 2013 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2013, IEEE , 2013, 104-112 p.Conference paper, Published paper (Refereed)
Abstract [en]

Today, coarse grained reconfigurable architectures (CGRAs) host multiple applications, with arbitrary communication and computation patterns. Each application itself is composed of multiple tasks, spatially mapped to different parts of platform. Providing worst-case operating point to all applications leads to excessive energy and power consumption. To cater this problem, dynamic voltage and frequency scaling (DVFS) is a frequently used technique. DVFS allows to scale the voltage and/or frequency of the device, based on runtime constraints. Recent research suggests that the efficiency of DVFS can be significantly enhanced by combining dynamic parallelism with DVFS. The proposed methods exploit the speedup induced by parallelism to allow aggressive frequency and voltage scaling. These techniques, employ greedy algorithm, that blindly parallelizes a task whenever required resources are available. Therefore, it is likely to parallelize a task(s) even if it offers no speedup to the application, thereby undermining the effectiveness of parallelism. As a solution to this problem, we present energy aware task parallelism. Our solution relies on a resource allocation graphs and an autonomous parallelism, voltage, and frequency selection algorithm. Using resource allocation graph, as a guide, the autonomous parallelism, voltage, and frequency selection algorithm parallelizes a task only if its parallel version reduces overall application execution time. Simulation results, using representative applications (MPEG4, WLAN), show that our solution promises better resource utilization, compared to greedy algorithm. Synthesis results (using WLAN) confirm a significant reduction in energy (up to 36%), power (up to 28%), and configuration memory requirements (up to 36%), compared to state of the art.

Place, publisher, year, edition, pages
IEEE , 2013. 104-112 p.
Keyword [en]
Application execution, Arbitrary communication, Coarse grained reconfigurable architecture (CGRAs), Configuration memory, Dynamic voltage and frequency scaling, Frequency selection, Multiple applications, Resource utilizations
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-132291DOI: 10.1109/SAMOS.2013.6621112ISI: 000332458100017Scopus ID: 2-s2.0-84888869658ISBN: 978-147990103-6 (print)OAI: oai:DiVA.org:kth-132291DiVA: diva2:659474
Conference
2013 13th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2013; Samos; Greece; 15 July 2013 through 18 July 2013
Note

QC 20140204

Available from: 2013-10-25 Created: 2013-10-25 Last updated: 2014-04-10Bibliographically approved

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Hemani, Ahmed

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Jafri, Syed Mohammad Asad HassanTajammul, Muhammad AdeelHemani, AhmedPaul, KolinTenhunen, Hannu
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