A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA
2013 (English)In: MES '13 Proceedings of the First International Workshop on Many-core Embedded Systems, ACM , 2013, 25-32 p.Conference paper (Refereed)
This paper presents a code generation method that translates an intermediate Register-Transfer Level (RTL) model of a system into its corresponding VHDL code for ASIC and FPGAs and MATLAB functions for manycores CGRAs. The intermediate representation consists of Function Implementation (FIMPs) and the glue logic. FIMPs are VHDL design units for the ASIC and FPGA implementation styles and MATLAB function templates for the CGRA implementation style, while the glue logic is a compact data structure storing Global Interconnect and Control (GLIC) information. The automatically generated implementation codes increase the resource usage by 1.5% on the average while reducing total design effort by two orders of magnitudes.
Place, publisher, year, edition, pages
ACM , 2013. 25-32 p.
code generation, function implementation, global interconnect and control, system-level synthesis
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-132292DOI: 10.1145/2489068.2489072ScopusID: 2-s2.0-84882284535ISBN: 978-145032063-4OAI: oai:DiVA.org:kth-132292DiVA: diva2:659476
1st International Workshop on Many-Core Embedded Systems, MES 2013, in Conjunction with the 40th Annual IEEE/ACM International Symposium on Computer Architecture, ISCA 2013; Tel-Aviv; Israel; 24 June 2013 through 24 June 2013
QC 201311132013-10-252013-10-252013-11-13Bibliographically approved