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Distributed Runtime Computation of Constraints for Multiple Inner Loops
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
Indian Institute of Technology, Delhi, India. (Department of Computer Science and engineering)
2013 (English)In: Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013, New York: IEEE , 2013, 389-395 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents hardware solution for runtime computation of loop constraints and synchronizing delays for multiple inner loops in parallel distributed implementation of digital signal processing sub-systems. Methods to map and generate the runtime computation code for loop constraints and synchronizing delays are also presented. Compared to the traditional methods, the proposed solution achieves 55% average code compaction and 32.7% average performance improvement. The solution has modest hardware cost that increases linearly with the dimension of the architecture and has no performance penalty. Results from multiple realistic examples are presented, analyzed and compared to the traditional methods.

Place, publisher, year, edition, pages
New York: IEEE , 2013. 389-395 p.
Keyword [en]
Streaming address generation, CGRA, Inner loop acceleration, Code compaction
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-132294DOI: 10.1109/DSD.2013.49ISI: 000337235200053Scopus ID: 2-s2.0-84890042733ISBN: 978-076955074-9 (print)OAI: oai:DiVA.org:kth-132294DiVA: diva2:659479
Conference
16th Euromicro Conference on Digital System Design, DSD 2013; Santander, Spain, 4-6 September 2013
Note

QC 20140211

Available from: 2013-10-25 Created: 2013-10-25 Last updated: 2016-04-28Bibliographically approved
In thesis
1. SiLago: Enabling System Level Automation Methodology to Design Custom High-Performance Computing Platforms: Toward Next Generation Hardware Synthesis Methodologies
Open this publication in new window or tab >>SiLago: Enabling System Level Automation Methodology to Design Custom High-Performance Computing Platforms: Toward Next Generation Hardware Synthesis Methodologies
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Place, publisher, year, edition, pages
Stockholm, Sweden: KTH Royal Institute of Technology, 2016. 56 p.
Series
TRITA-ICT, 2016:05
Keyword
System Level Synthesis, High Level Synthesis, VLSI Design Methodology, Brain-like Computation, Neuromorphic Hardware, Address Generation, Thread Level Parallelism
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-185787 (URN)978-91-7595-900-9 (ISBN)
Public defence
2016-05-17, Sal B, Electrum 229, Isafjordsgatan 22, Kista, Stockholm, 20:24 (English)
Opponent
Supervisors
Note

QC 20160428

Available from: 2016-04-28 Created: 2016-04-27 Last updated: 2016-04-28Bibliographically approved

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Hemani, Ahmed

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