Distributed Runtime Computation of Constraints for Multiple Inner Loops
2013 (English)In: Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013, New York: IEEE , 2013, 389-395 p.Conference paper (Refereed)
This paper presents hardware solution for runtime computation of loop constraints and synchronizing delays for multiple inner loops in parallel distributed implementation of digital signal processing sub-systems. Methods to map and generate the runtime computation code for loop constraints and synchronizing delays are also presented. Compared to the traditional methods, the proposed solution achieves 55% average code compaction and 32.7% average performance improvement. The solution has modest hardware cost that increases linearly with the dimension of the architecture and has no performance penalty. Results from multiple realistic examples are presented, analyzed and compared to the traditional methods.
Place, publisher, year, edition, pages
New York: IEEE , 2013. 389-395 p.
Streaming address generation, CGRA, Inner loop acceleration, Code compaction
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-132294DOI: 10.1109/DSD.2013.49ISI: 000337235200053ScopusID: 2-s2.0-84890042733ISBN: 978-076955074-9OAI: oai:DiVA.org:kth-132294DiVA: diva2:659479
16th Euromicro Conference on Digital System Design, DSD 2013; Santander, Spain, 4-6 September 2013
QC 201402112013-10-252013-10-252016-04-28Bibliographically approved