Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Thulium silicate interfacial layer for scalable high-k/metal gate stacks
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0003-0333-376X
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-6705-1660
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0002-5845-3032
2013 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 60, no 10, 3271-3276 p.Article in journal (Refereed) Published
Abstract [en]

Interfacial layer (IL) control in high-k/metal gate stacks is crucial in achieving good interface quality, mobility, and reliability. A process is developed for the formation of a thulium silicate IL that can be integrated as a replacement for conventional chemical oxide ILs in gate-last high-k/metal gate CMOS process. A straightforward process integration scheme for thulium silicate IL is demonstrated, based on self-limiting silicate formation in inert gas atmosphere and with good selectivity of the etching step. The thulium silicate IL is shown to provide 0.25~{!@~}0.15 nm equivalent oxide thickness of the IL while preserving excellent electrical quality of the interface with Si. An interface state density ~0.7-21011 cm-2eV-1 was obtained at flat-band condition, and the nFET and pFET subthreshold slopes were 70 mV/dec. The inversion layer mobility was 20% higher than for the reference SiOx/HfO2 gate stack. Specifically, the measured mobility values were 230 cm2/ Vs for nFET and 60 cm2/Vs for pFET devices, at an inversion charge density of 1013 cm?2 and at a total capacitance equivalent thickness of 1.6 nm.

Place, publisher, year, edition, pages
2013. Vol. 60, no 10, 3271-3276 p.
Keyword [en]
High-k, interfacial layer (IL), scaled EOT, thulium, TmSiO
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-133169DOI: 10.1109/TED.2013.2275744ISI: 000324928900040Scopus ID: 2-s2.0-84884793585OAI: oai:DiVA.org:kth-133169DiVA: diva2:660220
Funder
EU, European Research Council, 228229
Note

QC 20131029

Available from: 2013-10-29 Created: 2013-10-28 Last updated: 2017-12-06Bibliographically approved
In thesis
1. Integration of thulium silicate for enhanced scalability of high-k/metal gate CMOS technology
Open this publication in new window or tab >>Integration of thulium silicate for enhanced scalability of high-k/metal gate CMOS technology
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

High-k/metal gate stacks have been introduced in CMOS technology during the last decade in order to sustain continued device scaling and ever-improving circuit performance. Starting from the 45 nm technology node, the stringent requirements in terms of equivalent oxide thickness and gate current density have rendered the replacement of the conventional SiON/poly-Si stack unavoidable. Although Hf-based technology has become the de facto industry standard for high-k/metal gate MOSFETs, problematic long-term scalability has motivated the research of novel materials and solutions to fulfill the target performances expected of gate stacks in future technology nodes.

In this work, integration of a high-k interfacial layer has been identified as the most promising approach to improve gate dielectric scalability, since this technology presents the advantage of potential compatibility with both current Hf-based and plausible future higher-k materials. Thulium silicate has been selected as candidate material for integration as interfacial layer, thanks to its unique properties which enabled the development of a straightforward integration process achieving well-controlled and repeatable growth in the sub-nm thickness regime, a contribution of 0.25+-0.15 nm to the total EOT, and high quality of the interface with Si.

Compatibility with industry-standard CMOS integration flows has been kept as a top priority in the development of the new technology. To this aim, a novel ALD process has been developed and characterized, and a manufacturable process flow for integration of thulium silicate in a generic gate stack has been designed. The thulium silicate interfacial layer technology has been verified to be compatible with standard integration flows, and fabrication of high-k/metal gate MOSFETs with excellent electrical characteristics has been demonstrated.

The possibility to achieve high performance devices by integration of thulium silicate in current Hf-based technology has been specifically demonstrated, and the TmSiO/HfO2 dielectric stack has been shown to be compatible with the industrial requirements of operation in the sub-nm EOT range (down to 0.6 nm), reliable device operation over a 10 year expected lifetime, and compatibility with common threshold voltage control techniques. The thulium silicate interfacial layer technology has been especially demonstrated to be superior to conventional chemical oxidation in terms of channel mobility at sub-nm EOT, since the TmSiO/HfO2 dielectric stack achieved ~20% higher electron and hole mobility compared to state-of-the-art SiOx/HfO2 devices at the same EOT. Such performance enhancement can provide a strong advantage in the EOT-mobility trade-off which is commonly observed in scaled gate stacks, and has been linked by temperature and stress analyses to the higher physical thickness of the high-k interfacial layer, which results in attenuated remote phonon scattering compared to a SiOx interfacial layer achieving the same EOT.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2014. xv, 107 p.
Series
TRITA-ICT/MAP AVH, ISSN 1653-7610 ; 2014:06
Keyword
thulium, silicate, TmSiO, Tm2O3, interfacial layer, IL, CMOS, high-k, ALD
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Information and Communication Technology
Identifiers
urn:nbn:se:kth:diva-145116 (URN)978-91-7595-115-7 (ISBN)
Public defence
2014-05-27, Sal D, Forum, KTH, Isafjordsgatan 39, Kista, 10:00 (English)
Opponent
Supervisors
Note

QC 20140512

Available from: 2014-05-12 Created: 2014-05-08 Last updated: 2016-12-22Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Authority records BETA

Dentoni Litta, EugenioHellström, Per-Erik

Search in DiVA

By author/editor
Dentoni Litta, EugenioHellström, Per-ErikHenkel, ChristophÖstling, Mikael
By organisation
Integrated Devices and Circuits
In the same journal
IEEE Transactions on Electron Devices
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 181 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf