Characterization of thulium silicate interfacial layer for high-k/metal gate MOSFETs
2013 (English)In: 2013 14th International Conference On Ultimate Integration On Silicon (ULIS), IEEE , 2013, 122-125 p.Conference paper (Refereed)
The possibility of integrating thulium silicate as IL (interfacial layer) in scaled high-klmetal gate stacks is explored. Electrical properties of the silicate IL are investigated in MOS capacitor structures for the silicate formation temperature range 500-900 degrees C. Results are compared to lanthanum silicate. A CMOS-compatible process flow for silicate formation is demonstrated, providing EOT of the IL as low as 0.1-0.3 nm and interface state density at flatband below 2.10(11) cm(-2)eV(-1). The silicate IL is found to be compatible with both gate-last and gate-first process flows, with a maximum thermal budget of 1000 degrees C.
Place, publisher, year, edition, pages
IEEE , 2013. 122-125 p.
, International Conference on Ultimate Integration on Silicon, ISSN 2330-5738
TmSiO, LaSiO, silicate, interfacial layer, high-k
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-133499DOI: 10.1109/ULIS.2013.6523528ISI: 000325214300030ScopusID: 2-s2.0-84880323601ISBN: 978-1-4673-4802-7OAI: oai:DiVA.org:kth-133499DiVA: diva2:662094
14th International Conference on Ultimate Integration on Silicon (ULIS), MAR 19-21, 2013, Coventry, England
QC 201311062013-11-062013-11-062014-05-12Bibliographically approved