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Characterization of thulium silicate interfacial layer for high-k/metal gate MOSFETs
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0003-0333-376X
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-6705-1660
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0002-5845-3032
2013 (English)In: 2013 14th International Conference On Ultimate Integration On Silicon (ULIS), IEEE , 2013, 122-125 p.Conference paper, Published paper (Refereed)
Abstract [en]

The possibility of integrating thulium silicate as IL (interfacial layer) in scaled high-klmetal gate stacks is explored. Electrical properties of the silicate IL are investigated in MOS capacitor structures for the silicate formation temperature range 500-900 degrees C. Results are compared to lanthanum silicate. A CMOS-compatible process flow for silicate formation is demonstrated, providing EOT of the IL as low as 0.1-0.3 nm and interface state density at flatband below 2.10(11) cm(-2)eV(-1). The silicate IL is found to be compatible with both gate-last and gate-first process flows, with a maximum thermal budget of 1000 degrees C.

Place, publisher, year, edition, pages
IEEE , 2013. 122-125 p.
Series
International Conference on Ultimate Integration on Silicon, ISSN 2330-5738
Keyword [en]
TmSiO, LaSiO, silicate, interfacial layer, high-k
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-133499DOI: 10.1109/ULIS.2013.6523528ISI: 000325214300030Scopus ID: 2-s2.0-84880323601ISBN: 978-1-4673-4802-7 (print)OAI: oai:DiVA.org:kth-133499DiVA: diva2:662094
Conference
14th International Conference on Ultimate Integration on Silicon (ULIS), MAR 19-21, 2013, Coventry, England
Note

QC 20131106

Available from: 2013-11-06 Created: 2013-11-06 Last updated: 2014-05-12Bibliographically approved
In thesis
1. Integration of thulium silicate for enhanced scalability of high-k/metal gate CMOS technology
Open this publication in new window or tab >>Integration of thulium silicate for enhanced scalability of high-k/metal gate CMOS technology
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

High-k/metal gate stacks have been introduced in CMOS technology during the last decade in order to sustain continued device scaling and ever-improving circuit performance. Starting from the 45 nm technology node, the stringent requirements in terms of equivalent oxide thickness and gate current density have rendered the replacement of the conventional SiON/poly-Si stack unavoidable. Although Hf-based technology has become the de facto industry standard for high-k/metal gate MOSFETs, problematic long-term scalability has motivated the research of novel materials and solutions to fulfill the target performances expected of gate stacks in future technology nodes.

In this work, integration of a high-k interfacial layer has been identified as the most promising approach to improve gate dielectric scalability, since this technology presents the advantage of potential compatibility with both current Hf-based and plausible future higher-k materials. Thulium silicate has been selected as candidate material for integration as interfacial layer, thanks to its unique properties which enabled the development of a straightforward integration process achieving well-controlled and repeatable growth in the sub-nm thickness regime, a contribution of 0.25+-0.15 nm to the total EOT, and high quality of the interface with Si.

Compatibility with industry-standard CMOS integration flows has been kept as a top priority in the development of the new technology. To this aim, a novel ALD process has been developed and characterized, and a manufacturable process flow for integration of thulium silicate in a generic gate stack has been designed. The thulium silicate interfacial layer technology has been verified to be compatible with standard integration flows, and fabrication of high-k/metal gate MOSFETs with excellent electrical characteristics has been demonstrated.

The possibility to achieve high performance devices by integration of thulium silicate in current Hf-based technology has been specifically demonstrated, and the TmSiO/HfO2 dielectric stack has been shown to be compatible with the industrial requirements of operation in the sub-nm EOT range (down to 0.6 nm), reliable device operation over a 10 year expected lifetime, and compatibility with common threshold voltage control techniques. The thulium silicate interfacial layer technology has been especially demonstrated to be superior to conventional chemical oxidation in terms of channel mobility at sub-nm EOT, since the TmSiO/HfO2 dielectric stack achieved ~20% higher electron and hole mobility compared to state-of-the-art SiOx/HfO2 devices at the same EOT. Such performance enhancement can provide a strong advantage in the EOT-mobility trade-off which is commonly observed in scaled gate stacks, and has been linked by temperature and stress analyses to the higher physical thickness of the high-k interfacial layer, which results in attenuated remote phonon scattering compared to a SiOx interfacial layer achieving the same EOT.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2014. xv, 107 p.
Series
TRITA-ICT/MAP AVH, ISSN 1653-7610 ; 2014:06
Keyword
thulium, silicate, TmSiO, Tm2O3, interfacial layer, IL, CMOS, high-k, ALD
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Information and Communication Technology
Identifiers
urn:nbn:se:kth:diva-145116 (URN)978-91-7595-115-7 (ISBN)
Public defence
2014-05-27, Sal D, Forum, KTH, Isafjordsgatan 39, Kista, 10:00 (English)
Opponent
Supervisors
Note

QC 20140512

Available from: 2014-05-12 Created: 2014-05-08 Last updated: 2016-12-22Bibliographically approved

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Dentoni Litta, EugenioHellström, Per-Erik

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