Secure Key Storage Using State Machines
2013 (English)In: 2013 IEEE 43rd International Symposium On Multiple-Valued Logic (ISMVL 2013), IEEE Computer Society, 2013, 290-295 p.Conference paper (Refereed)
In hardware implementations of cryptographic systems, secret keys are commonly stored in an on-chip memory. This makes them prone to physical attacks, since the location of a memory on a chip in usually easy to spot. We propose to encode secret keys using a state machine which can be concealed in the rest of the logic on a chip. We present an heuristic algorithm which constructs a minimal state machine for a given set of secret keys. We show that, by using m-ary encoding, we are able to construct state machines which are smaller than the ones constructed using binary encoding. The presented algorithm is feasible for storing up to 1Mbits of random data.
Place, publisher, year, edition, pages
IEEE Computer Society, 2013. 290-295 p.
, International Symposium on Multiple-Valued Logic, ISSN 0195-623X
Secret key, secure storage, shift register, NLFSR, binary machine, random logic, memory, FPGA
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-133664DOI: 10.1109/ISMVL.2013.50ISI: 000325643000050ScopusID: 2-s2.0-84880752601ISBN: 978-1-4673-6067-8OAI: oai:DiVA.org:kth-133664DiVA: diva2:662787
IEEE 43rd International Symposium on Multiple-Valued Logic (ISMVL), MAY 22-24, 2013, Toyama, Japan
QC 201311082013-11-082013-11-082013-11-08Bibliographically approved