Mathematical formalisms for performance evaluation of networks-on-chip
2013 (English)In: ACM Computing Surveys, ISSN 0360-0300, E-ISSN 0010-4892, Vol. 45, no 3, 38- p.Article in journal (Refereed) Published
This article reviews four popular mathematical formalisms-queueing theory, network calculus, schedulability analysis, anddataflow analysis-and how they have been applied to the analysis of on-chip communication performance in Systems-on-Chip. The article discusses the basic concepts and results of each formalism and provides examples of how they have been used in Networks-on-Chip (NoCs) performance analysis. Also, the respective strengths and weaknesses of each technique and its suitability for a specific purpose are investigated. An open research issue is a unified analytical model for a comprehensive performance evaluation of NoCs. To this end, this article reviews the attempts that have been made to bridge these formalisms.
Place, publisher, year, edition, pages
2013. Vol. 45, no 3, 38- p.
Analytical modeling, Network-on-chip (NoC), Performance evaluation, System-on-chip (SoC)
IdentifiersURN: urn:nbn:se:kth:diva-134288DOI: 10.1145/2480741.2480755ISI: 000321212300014ScopusID: 2-s2.0-84880103807OAI: oai:DiVA.org:kth-134288DiVA: diva2:665826
QC 201311212013-11-212013-11-202013-12-05Bibliographically approved