On-Chip Area-Efficient Binary Sequence Storage
2013 (English)In: Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 2013, 325-326 p.Conference paper (Refereed)
On-chip storage of binary sequences normally require the use ofRead-Only Memories (ROMs). However, ROMs do not exploit ofthe fact that the stored information is accessed sequentially. Thispaper presents an area-efficient sequence storage technique basedon state machines. Experimental results show that the presentedmethod significantly outperforms previous approaches. The resultingstate machines are on average 54% smaller than ROMs storingthe same sequence.
Place, publisher, year, edition, pages
2013. 325-326 p.
binary machine, built-in self-test, cryptography, lfsr, rom, sequence generation, Area-Efficient, Binary machines, On-chip storage, Read-only memory, State machine, Storage technique, Built-in self test, Integrated circuit testing, Binary sequences
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-136337DOI: 10.1145/2483028.2483124ScopusID: 2-s2.0-84878210501ISBN: 9781450319027OAI: oai:DiVA.org:kth-136337DiVA: diva2:675825
23rd ACM International Conference of the Great Lakes Symposium on VLSI, GLSVLSI 2013, 2 May 2013 through 3 May 2013, Paris
QC 201312062013-12-042013-12-042013-12-06Bibliographically approved