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On-Chip Area-Efficient Binary Sequence Storage
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0001-7382-9408
2013 (English)In: Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 2013, 325-326 p.Conference paper, Published paper (Refereed)
Abstract [en]

On-chip storage of binary sequences normally require the use ofRead-Only Memories (ROMs). However, ROMs do not exploit ofthe fact that the stored information is accessed sequentially. Thispaper presents an area-efficient sequence storage technique basedon state machines. Experimental results show that the presentedmethod significantly outperforms previous approaches. The resultingstate machines are on average 54% smaller than ROMs storingthe same sequence.

Place, publisher, year, edition, pages
2013. 325-326 p.
Keyword [en]
binary machine, built-in self-test, cryptography, lfsr, rom, sequence generation, Area-Efficient, Binary machines, On-chip storage, Read-only memory, State machine, Storage technique, Built-in self test, Integrated circuit testing, Binary sequences
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-136337DOI: 10.1145/2483028.2483124Scopus ID: 2-s2.0-84878210501ISBN: 9781450319027 (print)OAI: oai:DiVA.org:kth-136337DiVA: diva2:675825
Conference
23rd ACM International Conference of the Great Lakes Symposium on VLSI, GLSVLSI 2013, 2 May 2013 through 3 May 2013, Paris
Funder
Vinnova, 2011-03336
Note

QC 20131206

Available from: 2013-12-04 Created: 2013-12-04 Last updated: 2013-12-06Bibliographically approved

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Dubrova, Elena

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CiteExportLink to record
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Citation style
  • apa
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  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
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  • asciidoc
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