A Markovian performance model for networks-on-chip
2007 (English)In: Proceedings of the 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing, 2007, 157-164 p.Conference paper (Refereed)
Network-on-Chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Thus, it is of crucial importance for a designer to have access to fast methods for evaluating the performance of on-chip network. To this end, we present a Markovian model for evaluating the latency and energy consumption of on-chip networks, We compute the average delay due to path contention, virtual channel and crossbar switch arbitration using a queuing-based approach, which can capture the blocking phenomena of wormhole switching quite accurately. The model is then used to estimate the power consumption of all routers m NoCs The performance results from the analytical models are validated with those obtained from a synthesizable VHDL-based cycle accurate simulator Comparison with simulation results indicate that the proposed analytical model quite accurate and can be used as an efficient design tool by SoC designers.
Place, publisher, year, edition, pages
2007. 157-164 p.
, Euromicro Workshop on Parallel and Distributed Processing, ISSN 1066-6192
IdentifiersURN: urn:nbn:se:kth:diva-136400DOI: 10.1109/PDP.2008.83ISI: 000254266500022ScopusID: 2-s2.0-47349131822ISBN: 978-0-7695-3089-5OAI: oai:DiVA.org:kth-136400DiVA: diva2:675968
16th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, FEB 13-15, 2008, Toulouse, FRANCE
QC 201312052013-12-052013-12-052013-12-05Bibliographically approved