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PERMAP: A Performance-Aware Mapping for Application-Specific SoCs
2008 (English)In: 2008 International Conference on Application-Specific Systems, Architectures and Processors, 2008, 73-78 p.Conference paper, Published paper (Refereed)
Abstract [en]

Future System-on-Chip (SoC) designs will need efficient on-chip communication architectures that can provide efficient and scalable data transport among the Intellectual Properties (IPs). Designing and optimizing SoCs is an increasingly difficult task due to the size and complexity of the SoC design space, high cost of detailed simulation, and several constraints that the design must satisfy. For efficient design of SoCs, an efficient mapping of IPs onto Networks-on-Chip (NoCs) is highly desirable. Towards this end, we have presented PERMAP, a PERformance-aware MAPping algorithm which maps the IPs onto a generic NoC architecture such that the average communication delay is minimized This is accomplished by a performance analytical model which can be used for any arbitrary network topology with wormhole routing, The algorithm is used for mapping a video application onto a tile-based NoC and experimental results show that PERMAP is fast and robust.

Place, publisher, year, edition, pages
2008. 73-78 p.
Series
IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, ISSN 1063-6862
National Category
Computer Science
Identifiers
URN: urn:nbn:se:kth:diva-136401DOI: 10.1109/ASAP.2008.4580157ISI: 000260566200013Scopus ID: 2-s2.0-51649113422ISBN: 978-1-4244-1897-8 (print)OAI: oai:DiVA.org:kth-136401DiVA: diva2:675969
Conference
19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, JUL 02-04, 2008, Leuven, BELGIUM
Note

QC 20131205

Available from: 2013-12-05 Created: 2013-12-05 Last updated: 2013-12-05Bibliographically approved
In thesis
1. Performance Analysis and Design Space Exploration of On-Chip Interconnection Networks
Open this publication in new window or tab >>Performance Analysis and Design Space Exploration of On-Chip Interconnection Networks
2013 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The advance of semiconductor technology, which has led to more than one billion transistors on a single chip, has enabled designers to integrate dozens of IP (intellectual property) blocks together with large amounts of embedded memory. These advances, along with the fact that traditional communication architectures do not scale well have led to significant changes in the architecture and design of integrated circuits. One solution to these problems is to implement such a complex system using an on-chip interconnection network or network-on-chip (NoC). The multiple concurrent connections of such networks mean that they have extremely high bandwidth. Regularity can lead to design modularity providing a standard interface for easier component reuse and improved interoperability.

The present thesis addresses the performance analysis and design space exploration of NoCs using analytical and simulation-based performance analysis approaches. At first, we developed a simulator aimed to performance analysis of interconnection networks. The simulator is then used to evaluate the performance of networks topologies and routing algorithms since their choice heavily affect the performance of NoCs. Then, we surveyed popular mathematical formalisms – queueing theory, network calculus, schedulability analysis, and dataflow analysis – and how they have been applied to the analysis of on-chip communication performance in NoCs. We also addressed research problems related to modelling and design space exploration of NoCs.

In the next step, analytical router models were developed that analyse NoC performance. In addition to providing aggregate performance metrics such as latency and throughput, our approach also provides feedback about the network characteristics at a fine-level of granularity. Our approach explicates the impact that various design parameters have on the performance, thereby providing invaluable insight into NoC design. This makes it possible to use the proposed models as a powerful design and optimisation tool.

We then used the proposed analytical models to address the design space exploration and optimisation problem. System-level frameworks to address the application mapping and to design routing algorithms for NoCs were presented. We first formulated an optimisation problem of minimizing average packet latency in the network, and then solved this problem using the simulated annealing heuristic. The proposed framework can also address other design space exploration problems such as topology selection and buffer dimensioning.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2013. xxi, 37 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 13:21
National Category
Computer Science
Identifiers
urn:nbn:se:kth:diva-136409 (URN)978-91-7501-923-9 (ISBN)
Public defence
2013-12-18, Sal/Hall D, Forum, KTH-ICT, Isafjordsgatan 39, Kista, 13:00 (English)
Opponent
Supervisors
Note

QC 20131205

Available from: 2013-12-05 Created: 2013-12-05 Last updated: 2013-12-05Bibliographically approved

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