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Caspian: A tunable performance model for multi-core systems
2008 (English)In: 14th International Euro-Par Conference, Euro-Par 2008, 2008, 100-109 p.Conference paper, Published paper (Refereed)
Abstract [en]

Performance evaluation is an important engineering tool that provides valuable feedback on design choices in the implementation of multi-core systems such as parallel systems, multicomputers, and Systems-on-Chip (SoCs). The significant advantage of analytical models over simulation is that they can be used to obtain performance results for large systems under different configurations and working conditions which may not be feasible to study using simulation on conventional computers due to the excessive computation demands. We present Caspian(1), a novel analytic performance model, aimed to minimize prediction cost, while providing prediction accuracy. This is accomplished by using a G/G/1 priority queueing model which is used for arbitrary network topology with wormhole routing under arbitrary traffic pattern. The accuracy of this model is examined through extensive simulation results.

Place, publisher, year, edition, pages
2008. 100-109 p.
Series
Lecture Notes in Computer Science, ISSN 0302-9743 ; 5168
Keyword [en]
performance evaluation, analytical model, multi-core systems, G/G/1 queueing model
National Category
Computer Science
Identifiers
URN: urn:nbn:se:kth:diva-136402DOI: 10.1007/978-3-540-85451-7_12ISI: 000259084900009Scopus ID: 2-s2.0-51849140540ISBN: 978-3-540-85450-0 (print)OAI: oai:DiVA.org:kth-136402DiVA: diva2:675972
Conference
14th International Euro-Par Conference, AUG 26-29, 2008, Las Palmas de Gran Canaria, SPAIN
Note

QC 20131205

Available from: 2013-12-05 Created: 2013-12-05 Last updated: 2013-12-05Bibliographically approved
In thesis
1. Performance Analysis and Design Space Exploration of On-Chip Interconnection Networks
Open this publication in new window or tab >>Performance Analysis and Design Space Exploration of On-Chip Interconnection Networks
2013 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The advance of semiconductor technology, which has led to more than one billion transistors on a single chip, has enabled designers to integrate dozens of IP (intellectual property) blocks together with large amounts of embedded memory. These advances, along with the fact that traditional communication architectures do not scale well have led to significant changes in the architecture and design of integrated circuits. One solution to these problems is to implement such a complex system using an on-chip interconnection network or network-on-chip (NoC). The multiple concurrent connections of such networks mean that they have extremely high bandwidth. Regularity can lead to design modularity providing a standard interface for easier component reuse and improved interoperability.

The present thesis addresses the performance analysis and design space exploration of NoCs using analytical and simulation-based performance analysis approaches. At first, we developed a simulator aimed to performance analysis of interconnection networks. The simulator is then used to evaluate the performance of networks topologies and routing algorithms since their choice heavily affect the performance of NoCs. Then, we surveyed popular mathematical formalisms – queueing theory, network calculus, schedulability analysis, and dataflow analysis – and how they have been applied to the analysis of on-chip communication performance in NoCs. We also addressed research problems related to modelling and design space exploration of NoCs.

In the next step, analytical router models were developed that analyse NoC performance. In addition to providing aggregate performance metrics such as latency and throughput, our approach also provides feedback about the network characteristics at a fine-level of granularity. Our approach explicates the impact that various design parameters have on the performance, thereby providing invaluable insight into NoC design. This makes it possible to use the proposed models as a powerful design and optimisation tool.

We then used the proposed analytical models to address the design space exploration and optimisation problem. System-level frameworks to address the application mapping and to design routing algorithms for NoCs were presented. We first formulated an optimisation problem of minimizing average packet latency in the network, and then solved this problem using the simulated annealing heuristic. The proposed framework can also address other design space exploration problems such as topology selection and buffer dimensioning.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2013. xxi, 37 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 13:21
National Category
Computer Science
Identifiers
urn:nbn:se:kth:diva-136409 (URN)978-91-7501-923-9 (ISBN)
Public defence
2013-12-18, Sal/Hall D, Forum, KTH-ICT, Isafjordsgatan 39, Kista, 13:00 (English)
Opponent
Supervisors
Note

QC 20131205

Available from: 2013-12-05 Created: 2013-12-05 Last updated: 2013-12-05Bibliographically approved

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