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A Faster Shift Register Alternative to Filter Generators
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-2962-5509
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0001-7382-9408
2013 (English)In: Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013, IEEE , 2013, 713-718 p.Conference paper, Published paper (Refereed)
Abstract [en]

LFSR-based filter generators are used as a basic building block in many stream ciphers. Filter generators are popular because their well-defined mathematical description enables a detailed formal security analysis. In this paper, we show how to modify a filter generator into a nonlinear feedback shift register which is faster, but slightly larger, than the original filter generator. For example, the propagation delay can be reduced 1.54 times at the expense of 1.27% extra area. The presented method might be important for applications which require very high data rates, e.g. 4G mobile communication technology.

Place, publisher, year, edition, pages
IEEE , 2013. 713-718 p.
Keyword [en]
Cryptography security, NLFSR, Propagation delay
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:kth:diva-138550DOI: 10.1109/DSD.2013.81ISI: 000337235200098Scopus ID: 2-s2.0-84890017929ISBN: 978-076955074-9 (print)OAI: oai:DiVA.org:kth-138550DiVA: diva2:681347
Conference
16th Euromicro Conference on Digital System Design, DSD 2013; Santander; Spain; 4 September 2013 through 6 September 2013
Funder
Swedish Foundation for Strategic Research
Note

QC 20140305

Available from: 2013-12-19 Created: 2013-12-19 Last updated: 2015-11-20Bibliographically approved
In thesis
1. Analysis and Synthesis of Boolean Networks
Open this publication in new window or tab >>Analysis and Synthesis of Boolean Networks
2015 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

In this thesis, we present techniques and algorithms for analysis and synthesis of synchronous Boolean and multiple-valued networks.

Synchronous Boolean and multiple-valued networks are a discrete-space discrete-time model of gene regulatory networks. Their cycle of states, called \emph{attractors}, are believed to give a good indication of the possible functional modes of the system. This motivates research on algorithms for finding attractors. Existing decision diagram-based approaches have limited capacity due to the excessive memory requirements of decision diagrams. Simulation-based approaches can be applied to large networks, however, their results are incomplete. In the first part of this thesis, we present an algorithm, which uses a SAT-based bounded model checking approach to find all attractors in a multiple-valued network. The efficiency of the presented algorithm is evaluated by analysing 30 network models of real biological processes as well as \num{35000} randomly generated 4-valued networks. The results show that our algorithm has a potential to handle an order of magnitude larger models than currently possible. One of the characteristic features of genetic regulatory networks is their inherent robustness, that is, their ability to retain functionality in spite of the introduction of random faults. In the second part of this thesis, we focus on the robustness of a special kind of Boolean networks called \emph{Balanced Boolean Networks} (BBNs). We formalize the notion of robustness and introduce a method to construct \emph{BBNs} for $2$-singleton attractors Boolean networks. The experiment results show that \emph{BBNs} are capable of tolerating single stuck-at faults. Our method improves the robustness of random Boolean networks by at least $13\%$ on average, and in some special case, up to $61\%$.

In the third part of this thesis, we focus on a special type of synchronous Boolean networks, namely Feedback Shift Registers (FSRs). FSR-based filter generators are used as a basic building block in many cryptographic systems, e.g. stream ciphers. Filter generators are popular because their well-defined mathematical description enables a detailed formal security analysis. We show how to modify a filter generator into a nonlinear FSR, which is faster, but slightly larger, than the original filter generator. For example, the propagation delay can be reduced 1.54 times at the expense of 1.27\% extra area. The presented method might be important for applications, which require very high data rates, e.g. 5G mobile communication technology.

In the fourth part of this thesis, we present a new method for detecting and correcting transient faults in FSRs based on duplication and parity checking. Periodic fault detection of functional circuits is very important for cryptographic systems because a random hardware fault can compromise their security.

The presented method is more reliable than Triple Modular Redundancy (TMR) for large FSRs, while the area overhead of the two approaches are comparable. The presented approach might be important for cryptographic systems using large FSRs.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. xi, 57 p.
Series
TRITA-ICT, 2015:23
National Category
Computer Systems
Identifiers
urn:nbn:se:kth:diva-177138 (URN)978-91-7595-770-8 (ISBN)
Presentation
2015-12-18, Sla B, Electrum, KTH-ICT, Kista, 09:00 (English)
Opponent
Supervisors
Note

QC 20151120

Available from: 2015-11-20 Created: 2015-11-16 Last updated: 2015-11-20Bibliographically approved

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Liu, MingDubrova, Elena

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