Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Analysis and evaluation of circuit switched NoC and packet switched NoC
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0001-7966-6128
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
2013 (English)In: Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013, IEEE , 2013, 21-28 p.Conference paper, Published paper (Refereed)
Abstract [en]

Circuit switched NoC has, compared to packet switching, a longer setup time, guaranteed throughput and latency, higher clock frequency, lower HW complexity, and higher energy efficiency. Depending on packet size and throughput requirements they exhibit better or worse performance. In this paper we designed a circuit switched NoC and compared that with packet switched NoC. By speculation and analysis, we propose that, as packet size increases, performance decreases for packet switched NoC, while it increases for circuit switched NoC. By close examination on the router architecture, we suggest that circuit switched NoC can operate at a higher clock frequency than packet switched NoC, and thus at zero load above a certain packet size circuit switched NoC could be better than packet switched NoC in packet delay. Experiment results support our intuitions and analysis. We find the cross-over point, above which circuit switching has lower latency, is around 30 flits/packet under low load and 60-70 flits/packet under high network load.

Place, publisher, year, edition, pages
IEEE , 2013. 21-28 p.
Series
IEEE International Conference on Robotics and Automation, ISSN 1050-4729
Keyword [en]
Analysis and evaluation, Circuit switching, Clock frequency, Guaranteed throughputs, Network load, Packet delay, Packet-switched, Router architecture
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-139421DOI: 10.1109/DSD.2013.13ISI: 000337235200003Scopus ID: 2-s2.0-84890067489ISBN: 978-076955074-9 (print)OAI: oai:DiVA.org:kth-139421DiVA: diva2:688334
Conference
16th Euromicro Conference on Digital System Design, DSD 2013; Santander; Spain; 4 September 2013 through 6 September 2013
Note

QC 20140116

Available from: 2014-01-16 Created: 2014-01-13 Last updated: 2015-11-09Bibliographically approved
In thesis
1. New circuit switching techniques in on-chip networks
Open this publication in new window or tab >>New circuit switching techniques in on-chip networks
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Network on Chip (NoC) is proposed as a promising technology to address the communication challenges in deep sub-micron era. NoC brings network-based communication into the on-chip environment and tackles the problems like long wire complexities, bandwidth scaling and so on. After more than a decade's evolution and development, there are many NoC architectures and solutions available. Nevertheless, NoCs can be classi_ed into two categories: packet switched NoC and circuit switched NoC. In this thesis, targeting circuit switched NoC, we present our innovations and considerations on circuit switched NoCs in three areas, namely, connection setup method, time division multiplexing (TDM) technology and spatial division multiplexing (SDM) technology.

Connection setup technique deeply inuences the architecture and performance of a circuit switched NoC, since circuit switched NoC requires to set up connections before launching data transfer. We propose a novel parallel probe based method for dynamic distributed connection setup. This setup method on one hand searches all the possible minimal paths in parallel. On the other hand, it also has a mechanism to reduce resource occupation during the path search process by reclaiming redundant paths. With this setup method, connections are more likely to be established because of the exploration on the path diversity.

TDM based NoC constitutes a sub-category of circuit switched NoC. We propose a double time-wheel technique to facilitate a probe based connection setup in TDM NoCs. With this technique, path search algorithms used in connection setup are no longer limited to deterministic routing algorithms. Moreover, the hardware cost can be reduced, since setup requests and data flows can co-exist in one network. Apart from the double time-wheel technique for connection setup, we also propose a highway technique that can enhance the slot utilization during data transfer. This technique can accelerate the transfer of a data flow while maintaining the throughput guarantee and the packet order.

SDM based NoC constitutes another sub-category of circuit switched NoC. SDM NoC can benefit from high clock frequency and simple synchronization efforts. To better support the dynamic connection setup in SDM NoCs, we design a single cycle allocator for channel allocation inside each router. This allocator can guarantee both strong fairness and maximal matching quality. We also build up a circuit switched NoC, which can support multiple channels and multiple networks, to study different ways of organizing channels and setting up connections. Finally, we make a comparison between circuit switched NoC and packet switched NoC. We show the strengths and weaknesses on each of them by analysis and evaluation.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. xvi, 82 p.
Series
TRITA-ICT-ECS AVH, ISSN 1653-6363 ; 2015:18
National Category
Computer Systems
Identifiers
urn:nbn:se:kth:diva-176624 (URN)978-91-7595-727-2 (ISBN)
Public defence
2015-12-04, Sal A, Elektrum, KTH-ICT, Kista, 09:00 (English)
Opponent
Supervisors
Note

QC 20151109

Available from: 2015-11-09 Created: 2015-11-09 Last updated: 2015-11-09Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Authority records BETA

Liu, ShaotengLu, Zhonghai

Search in DiVA

By author/editor
Liu, ShaotengJantsch, AxelLu, Zhonghai
By organisation
Electronic Systems
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 147 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf