Analysis and evaluation of circuit switched NoC and packet switched NoC
2013 (English)In: Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013, IEEE , 2013, 21-28 p.Conference paper (Refereed)
Circuit switched NoC has, compared to packet switching, a longer setup time, guaranteed throughput and latency, higher clock frequency, lower HW complexity, and higher energy efficiency. Depending on packet size and throughput requirements they exhibit better or worse performance. In this paper we designed a circuit switched NoC and compared that with packet switched NoC. By speculation and analysis, we propose that, as packet size increases, performance decreases for packet switched NoC, while it increases for circuit switched NoC. By close examination on the router architecture, we suggest that circuit switched NoC can operate at a higher clock frequency than packet switched NoC, and thus at zero load above a certain packet size circuit switched NoC could be better than packet switched NoC in packet delay. Experiment results support our intuitions and analysis. We find the cross-over point, above which circuit switching has lower latency, is around 30 flits/packet under low load and 60-70 flits/packet under high network load.
Place, publisher, year, edition, pages
IEEE , 2013. 21-28 p.
, IEEE International Conference on Robotics and Automation, ISSN 1050-4729
Analysis and evaluation, Circuit switching, Clock frequency, Guaranteed throughputs, Network load, Packet delay, Packet-switched, Router architecture
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-139421DOI: 10.1109/DSD.2013.13ISI: 000337235200003ScopusID: 2-s2.0-84890067489ISBN: 978-076955074-9OAI: oai:DiVA.org:kth-139421DiVA: diva2:688334
16th Euromicro Conference on Digital System Design, DSD 2013; Santander; Spain; 4 September 2013 through 6 September 2013
QC 201401162014-01-162014-01-132015-11-09Bibliographically approved