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Power-Aware Dynamic Memory Management on Many-Core Platforms Utilizing DVFS
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
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2013 (English)In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 13, no 1, 40- p.Article in journal (Refereed) Published
Abstract [en]

Today multicore platforms are already prevalent solutions for modern embedded systems. In the future, embedded platforms will have an even more increased processor core count, composing many-core platforms. In addition, applications are becoming more complex and dynamic and try to efficiently utilize the amount of available resources on the embedded platforms. Efficient memory utilization is a key challenge for application developers, especially since memory is a scarce resource and often becomes the system's bottleneck. To cope with this dynamism and achieve better memory footprint utilization (lowmemory fragmentation) application developers resort to the usage of dynamic memory (heap) management techniques, by allocating and deallocating data at runtime. Moreover, overall power consumption is another key challenge that needs to be taken into consideration. Towards this, designers employ the usage of Dynamic Voltage and Frequency Scaling (DVFS) mechanisms, adapting to the application's computational demands at runtime. In this article, we propose the combination of dynamic memory management techniques with DVFS ones. This is performed by integrating, within thememorymanager, runtimemonitoringmechanisms that steer the DVFSmechanisms to adjust clock frequency and voltage supply based on heap performance. The proposed approach has been evaluated on a distributed shared-memory many-core platform composed of multiple LEON3 processors interconnected by a Network-on-Chip infrastructure, supporting DVFS. Experimental results show that by using the proposed method for monitoring and applying DVFS mechanisms the power consumption concerning dynamic memory management was reduced by approximately 37%. In addition we present the trade-offs the proposed approach. Last, by combining the developed method with heap fragmentation-aware dynamic memory managers, we achieve low heap fragmentation values combined with low power consumption.

Place, publisher, year, edition, pages
2013. Vol. 13, no 1, 40- p.
Keyword [en]
Dynamic memory management, Dynamic voltage and frequency scaling, Many-core system-on-chip, Performance-energy trade-offs
National Category
Computer and Information Science
URN: urn:nbn:se:kth:diva-139996DOI: 10.1145/2536747.2536762ISI: 000329135500015ScopusID: 2-s2.0-84890324254OAI: diva2:688693
EU, FP7, Seventh Framework Programme, FP7-215244 MOSART FP7-ICT-2009-4-248716 2PARMA

QC 20140117

Available from: 2014-01-17 Created: 2014-01-16 Last updated: 2014-01-23Bibliographically approved

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