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An improved transmission scheme for error-prone inter-chip Network-on-Chip communication links implemented on FPGAs
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0002-8072-1742
2013 (English)In: 10th FPGAworld Conference - Academic Proceedings 2013, FPGAworld 2013, 2013Conference paper (Refereed)
Abstract [en]

Network-on-Chip (NoC) is an alternative to traditional busses for faster interconnect mechanism. The aim is to have infinite scalability, and this implies the possibility to extend the on-chip NoC communication protocol off-chip. To gain wholesome advantage of Network-on-Chip (NoC), off-chip extensions should also have similar communication throughput compared to the on-chip network. Faster data-rate is the single most demanded requirement of modern applications. There is a continuous drive to fulfill this escalating demand as much as possible. Two of the most prominent limiting factors in achieving this purpose are 'reduced accuracy' and 'protocol handling', especially in case of systems which do not have synchronous communication. Efficient optimizations are needed in multiple areas to upgrade the speed of data transfer. This paper presents an improved off-chip network solution to a slower and error-prone board-bridge part of a Network-on-Chip (NoC). The new solution increases the accuracy and speed of the plesiochronous off-chip extension to the NoC. The Network-on-Chip has 16 processor-nodes implemented on four interconnected plesiochronous Altera Stratix-II FPGA boards in 4x4 configuration in such a way that each board hosts a Quad-core NoC.

Place, publisher, year, edition, pages
Keyword [en]
Built-in Self Test, Interconnect, Multi-core, Network-on-Chip, Off-chip/inter-board NoC protocol, On-chip NoC protocol, Plesiochronous clocking, Multi core, Network on chip, Off-chip, On chips, Data transfer, Digital storage, Field programmable gate arrays (FPGA), Microprocessor chips, Servers, VLSI circuits
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-140020DOI: 10.1145/2513683.2513691ScopusID: 2-s2.0-84885903972ISBN: 9781450324960OAI: diva2:689900
10th FPGAworld Conference, FPGAworld 2013; Stockholm; Sweden; 10 September 2013 through 12 September 2013

QC 20140122

Available from: 2014-01-22 Created: 2014-01-16 Last updated: 2014-01-22Bibliographically approved

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