Development of New Metallization Processes for High Aspect Ratio Through-Silicon-Via (TSV) for Gas Sensor Applications
Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
This project is related to Through-Silicon-Via (TSV) technology, and in particular to providing TSVs with high aspect ratio in substrates together with self-aligned routing structures on the surfaces of the substrate, in order to make so called interposers and 3D MEMS. The goal of this project is to investigate and develop new metallization technique, create connections from front to back of silicon wafer using High Aspect Ratio (HAR) Through-Silicon-Vias suitable for easier gas sensor packaging.
The metallization scheme this project focused on is primarily electroless plating of nickel (Ni) and copper (Cu). Three different types of wafers are used in this project with different objectives; i) plan wafers (no vias present) used to optimize the overall process and especially solving adhesion issues that Silex previously faced when making first experiments in 2011, ii) TSV wafers to create a conformal and smooth seed-layer on HAR via structures and finally iii) patterned wafers to selectively deposit the self-aligned routing structures.
Different plating experiments according to DOE have been performed to fulfill the objectives of this project: i) adhesion: best results obtained using a silicidation process (Ni)Si by Rapid Thermal Annealing (heat treatment), ii) conformal HAR TSV seed-layer films obtained by electroless deposition of copper on electroless nickel verified by cross-section SEM, iii) a self aligned selectively deposited Ni/Cu Re-Distribution Layer (RDL) was obtained by using an oxide acting as the mask and patterned by lithography providing the exposed structures to be selectively deposited by electroless nickel and copper, iv) experiments done according to the objectives, verified that the conformal Ni/Cu electroless deposited films are useful as seed-layer for thick electroplated conventional TSV processing at Silex.
The electroless copper process used so far has film thickness limitations and could not yet been applied to completely fill the vias when thicker than 10 8m of Cu is needed. It is recommended to further study this issue.
Even though the project achieved the specific goals, there is still room for further improvement and several potential future improvements are suggested to enable the integration of the developed technologies into fully tested HAR TSV interposers.
Place, publisher, year, edition, pages
2013. , 51 p.
TSV, Through-Silicon-Via, metallization, interposers, electroless plating
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-141115OAI: oai:DiVA.org:kth-141115DiVA: diva2:694739
Subject / course
Master of Science in Engineering - Microelectronics
Conference room at SIP, Osquldas väg 10, Stockholm (English)
Ebefors, Thorbjörn, Dr.Fredlund, Jessica
Niklaus, Frank, professor