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Analysis and Experimental Verification of the Influence of Fabrication Process Tolerances and Circuit Parasitics on Transient Current Sharing of Parallel-Connected SiC JFETs
KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.ORCID iD: 0000-0002-9850-9440
KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
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2014 (English)In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 29, no 5, 2180-2191 p.Article in journal (Refereed) Published
Abstract [en]

Operation of parallel-connected 4H-SiC vertical junction field effect transistors (VJFETs) from SemiSouth is modeled using numerical simulations and experimentally verified. The unbalanced current waveforms of parallel-connected VJFETs are investigated with respect to the spread in the critical parameters of the device structure and to the influence of the parasitic inductances in the measurement circuit. The device structures are reconstructed based on scanning electron microscopy (SEM) analysis, electrical characterization, and device simulations. The doping concentration and profile depth of a p-grid formed by angular implantation are studied as main contributors that influence the variation of the on-state characteristics, and the threshold voltage of the experimental devices. It has been shown elsewhere that similar differences in p-grid also lead to differences in gate-source breakdown voltage. The switching performance of the parallel-connected JFETs is measured using single and double gate drivers in a double-pulse test and compared with simulations. The switched current and voltage waveforms from measurements are reproduced in simulation by introducing the parasitics. From the analysis, it is found that reasonable differences in doping levels and profiles of the p-grid give rise to significant differences in device parameters. However, even with these parameter differences and circuit asymmetries, it is possible to successfully operate parallel-connected VJFETs of this type.

Place, publisher, year, edition, pages
IEEE , 2014. Vol. 29, no 5, 2180-2191 p.
Keyword [en]
Medici, parallel connection, silicon carbide (SiC), vertical junction field effect transistor (VJFET)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
SRA - Energy
Identifiers
URN: urn:nbn:se:kth:diva-141275DOI: 10.1109/TPEL.2013.2281084ISI: 000329991500005Scopus ID: 2-s2.0-84893148878OAI: oai:DiVA.org:kth-141275DiVA: diva2:696121
Funder
StandUp
Note

QC 20140213

Available from: 2014-02-13 Created: 2014-02-13 Last updated: 2017-12-06Bibliographically approved
In thesis
1. Simulation and Electrical Evaluation of 4H-SiC Junction Field Effect Transistors and Junction Barrier Schottky Diodes with Buried Grids
Open this publication in new window or tab >>Simulation and Electrical Evaluation of 4H-SiC Junction Field Effect Transistors and Junction Barrier Schottky Diodes with Buried Grids
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Silicon carbide (SiC) has higher breakdown field strength than silicon (Si), which enables thinner and more highly doped drift layers compared to Si. Consequently, the power losses can be reduced compared to Si-based power conversion systems. Moreover, SiC allows the power conversion systems to operate at high temperatures up to 250 oC. With such expectations, SiC is considered as the material of choice for modern power semiconductor devices for high efficiencies, high temperatures, and high power densities. Besides the material benefits, the typeof the power device also plays an important role in determining the system performance.

Compared to the SiC metal-oxide semiconductor field-effect transistor (MOSFET) and bipolar junction transistor (BJT), the SiC junction field-effect transistor (JFET) is a very promising power switch, being a voltage-controlled device without oxide reliability issues. Its channel iscontrolled by a p-n junction. However, the present JFETs are not optimized yet with regard to on-state resistance, controllability of threshold voltage, and Miller capacitance.

In this thesis, the state-of-the-art SiC JFETs are introduced with buried-grid (BG) technology.The buried grid is formed in the channel through epitaxial growth and etching processes. Through simulation studies, the new concepts of normally-on and -off BG JFETs with 1200 V blocking capability are investigated in terms of static and dynamic characteristics. Additionally, two case studies are performed in order to evaluate total losses on the system level. These investigations can be provided to a power circuit designer for fully exploiting the benefit of power devices. Additionally, they can serve as accurate device models and guidelines considering the switching performance.

The BG concept utilized for JFETs has been also used for further development of SiC junctionbarrier Schottky (JBS) diodes. Especially, this design concept gives a great impact on high temperature operation due to efficient shielding of the Schottky interface from high electric fields. By means of simulations, the device structures with implanted and epitaxial p-grid formations, respectively, are compared regarding threshold voltage, blocking voltage, and maximum electric field at the Schottky interface. The results show that the device with an epitaxial grid can be more efficient at high temperatures than that with an implanted grid. To realize this concept, the device with implanted grid was optimized using simulations, fabricated and verified through experiments. The BG JBS diode clearly shows that the leakage current is four orders of magnitude lower than that of a pure Schottky diode at an operation temperature of 175 oC and 2 to 3 orders of magnitude lower than that of commercial JBS diodes.

Finally, commercialized vertical trench JFETs are evaluated both in simulations andexperiments, while it is important to determine the limits of the existing JFETs and study their performance in parallel operation. Especially, the influence of uncertain parameters of the devices and the circuit configuration on the switching performance are determined through simulations and experiments.

Abstract [sv]

Kiselkarbid (SiC) har en högre genombrottsfältstyrka än kisel, vilket möjliggör tunnare och mer högdopade driftområden jämfört med kisel. Följaktligen kan förlusterna reduceras jämfört med kiselbaserade omvandlarsystem. Dessutom tillåter SiC drift vid temperatures upp till 250 oC. Dessa utsikter gör att SiC anses vara halvledarmaterialet för moderna effekthalvledarkomponenter för hög verkningsgrad, hög temperature och hög kompakthet. Förutom materialegenskaperna är också komponenttypen avgörande för att bestämma systemets prestanda.

Jämfört med SiC MOSFETen och bipolärtransistorn i SiC är SiC JFETen en mycket lovande component, eftersom den är spänningsstyrd och saknar tillförlitlighetsproblem med oxidskikt. Dess kanal styrs an en PNövergång. Emellertid är dagens JFETar inte optimerade med hänseende till on-state resistans, styrbarhet av tröskelspänning och Miller-kapacitans.

I denna avhandling introduceras state-of-the-art SiC JFETar med buried-grid (BG) teknologi. Denna åstadkommes genom epitaxi och etsningsprocesser. Medelst simulering undersöks nya concept för normally-on och normally-off BG JFETar med blockspänningen 1200 V. Såvä statiska som dynamiska egenskper undersöks. Dessutom görs två fallstudier vad avser totalförluster på systemnivå. Dessa undersökningar kan vara värdefulla för en konstruktör för att till fullo utnyttja fördelarna av komponenterna. Dessutom kan resultaten från undersökningarna användas som komponentmodeller och anvisningar vad gäller switch-egenskaper.

BG konceptet som använts för JFETar har också använts för vidareutveckling av så kallade JBS-dioder. Speciellt ger denna konstruktion stora fördelar vid höga temperature genom en effektiv skärmning av Schottkyövergången mot höga elektriska fält. Genom simuleringar har komponentstrukturer med implanterade och epitaxiella grids jämförst med hänseende till tröskelspänning, genombrottspänning och maximalt elektriskt fält vid Schottky-övergången. Resultaten visar att den epitaxiella varianten kan vara mer effektiv än den implanterade vid höga temperaturer. För att realisera detta concept optimerades en komponent med implanterat grid med hjälp av simuleringar. Denna component tillverkades sedan och verifierades genom experiment. BG JBS-dioden visar tydligt att läckströmmen är fyra storleksordningar lägre än för en ren Schottky-diod vid 175 oC, och två till tre storleksordningar lägre än för kommersiella JBS-dioder.

Slutligen utvärderas kommersiella vertical trench-JFETar bade genom simuleringar och experiment, eftersom det är viktigt att bestämma gränserna för existerande JFETar och studera parallelkoppling. Speciellt studeras inverkan av obestämda parametrar och kretsens konfigurering på switchegenskaperna. Arbetet utförs bade genom simuleringar och experiment.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. xvi, 97 p.
Series
TRITA-EE, ISSN 1653-5146 ; 2015:025
Keyword
Silicon carbide (SiC), junction field-effect transistors (JFETs), junction barrier schottky diode (JBS), schottky barrier diode (SBD), buried-grid (BG) technology, simulation, implantation, epitaxial growth
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-173340 (URN)978-91-7595-684-8 (ISBN)
Public defence
2015-10-12, Kollegiesalen, Brinellvägen 8, KTH, Stockholm, 10:15 (English)
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Supervisors
Note

QC 20150915

Available from: 2015-09-15 Created: 2015-09-09 Last updated: 2015-09-15Bibliographically approved

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Lim, Jang-KwonNee, Hans-Peter

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