Design and Evaluation of Reduced Self-Capacitance Inductor in DC/DC Converters with Fast-Switching SiC Transistors
2014 (English)In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 29, no 5, 2492-2499 p.Article in journal (Refereed) Published
The paper presents an inductor with reduced self-capacitance, designed and evaluated with fast-switching SiC transistors in dc-dc converters. A conventional inductor with the same core and number of turns was also build for comparison. The two inductors are tested experimentally on two different 2 kW, 100 kHz dc-dc converters with silicon carbide switches-one with a junction field-effect transistor (JFET) and the other with a bipolar junction transistor (BJT). Replacing the conventional inductor with the one that has lower self-capacitance improved the switching performance of the converter and reduced its electromagnetic emissions. Furthermore, the efficiency of the converter is improved-in the case of the JFET boost converter the power losses were reduced by 16% and by 20% in the case of BJT.
Place, publisher, year, edition, pages
IEEE , 2014. Vol. 29, no 5, 2492-2499 p.
Electromagnetic interference, inductors, junction field-effect transistors (JFETs), parasitic capacitance, silicon carbide (SiC)
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject SRA - Energy
IdentifiersURN: urn:nbn:se:kth:diva-141279DOI: 10.1109/TPEL.2013.2281990ISI: 000329991500035ScopusID: 2-s2.0-84893052013OAI: oai:DiVA.org:kth-141279DiVA: diva2:696126
QC 201402132014-02-132014-02-132016-02-26Bibliographically approved