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A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
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2013 (English)In: 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013, IEEE , 2013, 6702365- p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper describes a powerful simulation platform that enables accurate simulations of numerous network configurations under realistic traffic patterns to predict the performance and power needs of a 3-D integrated system early in the design flow. The simulation platform can model virtually any sized 2-D or 3-D network configuration, providing low-cost and fast tradeoff evaluations of various systems architectures. The network simulator uses scalable RTL-level models that can be used for accurate power and timing analyses. We demonstrate the capability of our simulation model by analyzing the performance of various network topologies under spatio-temporal traffic patterns to show how the network topology can be adjusted to meet the performance requirements of a design before it is manufactured. The simulation results can be used to optimize the placement of cores and communication buses early in the flow. By using the model, standard applications such as mobile application processor, femto-cell base-stations on-chip and wide-IO TSV memory stacking can be simulated.

Place, publisher, year, edition, pages
IEEE , 2013. 6702365- p.
Series
IEEE International 3D Systems Integration Conference, ISSN 2164-0157
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-143176DOI: 10.1109/3DIC.2013.6702365ISI: 000333258200052Scopus ID: 2-s2.0-84893929548ISBN: 978-146736484-3 (print)OAI: oai:DiVA.org:kth-143176DiVA: diva2:705673
Conference
2013 IEEE International 3D Systems Integration Conference, 3DIC 2013; San Francisco, CA; United States; 2 October 2013 through 4 October 2013
Note

QC 20140317

Available from: 2014-03-17 Created: 2014-03-17 Last updated: 2015-12-21Bibliographically approved
In thesis
1. Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture
Open this publication in new window or tab >>Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Three-Dimensional (3D) integration of circuits based on die and wafer stacking using through-silicon-via is a critical technology in enabling "more-than-Moore", i.e. functional integration of devices beyond pure scaling ("more Moore"). In particular, the scaling from multi-core to many-core architecture is an excellent candidate for such integration. 3D systems design follows is a challenging and a complex design process involving integration of heterogeneous technologies. It is also expensive to prototype because the 3D industrial ecosystem is not yet complete and ready for low-cost mass production. Networks-on-Chip (NoCs) efficiently facilitates the communication of massively integrated cores on 3D many-core architecture. In this thesis scalability and performance issues of NoCs are explored in terms of architecture, organization and functionality of many-core systems.

First, we evaluate on-chip network performance in massively integrated many-core architecture when network size grows. We propose link and channel models to analyze the network traffic and hence the performance. We develop a NoC simulation framework to evaluate the performance of a deflection routing network as the architecture scales up to 1000 cores. We propose and perform comparative analysis of 3D processor-memory model configurations in scalable many-core architectures.

Second, we investigate how the deflection routing NoCs can be designed to maximize the benefit of the fast TSVs through clock pumping techniques. We propose multi-rate models for inter-layer communication. We quantify the performance benefit through cycle-accurate simulations for various configurations of 3D architectures.

Finally, the complexity of massively integrated many-core architecture by itself brings a multitude of design challenges such as high-cost of prototyping, increasing complexity of the technology, irregularity of the communication network, and lack of reliable simulation models. We formulate a zero-load average distance model that accurately predicts the performance of deflection routing networks in the absence of data flow by capturing the average distance of a packet with spatial and temporal probability distributions of traffic.

The thesis research goals are to explore the design space of vertical integration for many-core applications, and to provide solutions to 3D technology challenges through architectural innovations. We believe the research findings presented in the thesis work contribute in addressing few of the many challenges to the field of combined research in many-core architectural design and 3D integration technology.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2016. xviii, 80 p.
Series
TRITA-ICT, 2015:29
Keyword
Alpha-model, Average distance, B-Model, NoC, Zero-load predictive model, deflection routing, q-routing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-179694 (URN)978-91-7595-803-3 (ISBN)
Public defence
2016-01-20, Hall C, Electrum, Isafjordsgatan 26, 16440, Kista, 13:00 (English)
Opponent
Supervisors
Note

QC 20151221

Available from: 2015-12-21 Created: 2015-12-21 Last updated: 2015-12-21Bibliographically approved

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