Towards the generic reconfigurable accelerator: Algorithm development, core design, and performance analysis
2013 (English)Conference paper (Refereed)
Adoption of reconfigurable computing is limited in part by the lack of simplified, economic, and reusable solutions. The significant speedup and energy saving can increase performance but also design complexity; in particular for heterogeneous SoCs blending several CPUs, GPUs, and FPGA-Accelerator Cores. On the other hand, implementing complex algorithms in hardware requires modeling and verification, not only HDL generation. Most approaches are too specific without looking for reusability. Therefore, we present a solution based on: (1) a design methodology to develop algorithms accelerated in reconfigurable/non-reconfigurable IP-Cores, using common access tools, and contemplating verification from model to embedded software stages; (2) a generic accelerator core design that enables relocation and reuse almost independently of the algorithm, and data-flow driven execution models; and (3) a performance analysis of the acceleration mechanisms included in our system (i.e., accelerator core, burst I/O transfers, and reconfiguration pre-fetch). In consequence, the implemented system accelerates algorithms (e.g., FIR and Kalman filters) with speedups up to 3 orders of magnitude, compared to processor implementations.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2013. 1-6 p.
field programmable gate arrays, reconfigurable architectures, heterogeneous SoC, performance analysis, reconfigurable computing, Acceleration, Algorithm design and analysis, Hardware, MATLAB, algorithm development, design methodology, embedded system, hardware accelerator, partial and run-time reconfiguration, reconfiguration techniques, system-on-chip
Embedded Systems Other Electrical Engineering, Electronic Engineering, Information Engineering Computer Systems
IdentifiersURN: urn:nbn:se:kth:diva-143222DOI: 10.1109/ReConFig.2013.6732334ISI: 000349244200077ScopusID: 2-s2.0-84894465436OAI: oai:DiVA.org:kth-143222DiVA: diva2:706120
2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013; Cancun; Mexico
Byron Navas is funded by ESPE. QC 201406262014-03-192014-03-192015-12-04Bibliographically approved