System level synthesis of hardware for DSP applications using pre-characterized function implementations
2013 (English)In: 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), IEEE , 2013Conference paper (Refereed)
SYLVA is a system level synthesis framework that transforms DSP sub-systems modeled as synchronous data flow into hardware implementations in ASIC, FPGAs or CGRAs. SYLVA synthesizes in terms of pre-characterized function implementations (FTMPs). It explores the design space in three dimensions, number of FTMPs, type of FTMPs and pipeline parallelism between the producing and consuming FTMPs. We introduce timing and interface model of FTMPs to enable reuse and automatic generation of Global Interconnect and Control (GLIC) to glue the FTMPs together into a working system. SYLVA has been evaluated by applying it to five realistic DSP applications and results analyzed for design space exploration, efficacy in generating GLIC by comparing to manually generated GLIC and accuracy of design space exploration by comparing the area and energy costs considered during the design space exploration based on pre-characterized FIMPs and the final results.
Place, publisher, year, edition, pages
IEEE , 2013.
Design space exploration, Electronic system level synthesis, Reuse, Synchronous data flow, System level synthesis
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-143296DOI: 10.1109/CODES-ISSS.2013.6659003ScopusID: 2-s2.0-84892642437ISBN: 978-147991417-3OAI: oai:DiVA.org:kth-143296DiVA: diva2:706277
11th ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013; Montreal, QC; Canada; 29 September 2013 through 4 October 2013
QC 201403192014-03-192014-03-192014-03-19Bibliographically approved