Fabrication of a SiC double gate vertical channel jfet and it's application in power electronics
2012 (English)In: Gallium nitride and silicon carbide power technologies 2, Electrochemical Society, 2012, no 3, 45-52 p.Conference paper (Refereed)
The fabrication process of an innovative epitaxial trench JFET with vertical channel and double gate control is reviewed. Due to the excellent doping and thickness control of the epitaxial regrowth techniques, the sub-micron channel can be tailored for normally-on and -off operation. Due to the vertical channel design the epitaxial trench JFETs have narrow cell pitch for high-density power integration and high saturation current capabilities. The excellent performance of these fabricated and packaged JFET devices is demonstrated with on-wafer measurements and power switching tests. High current conduction tests are performed at room temperature and elevated temperatures of 125°C with switching frequencies of 30 kHz and 200 kHz.
Place, publisher, year, edition, pages
Electrochemical Society, 2012. no 3, 45-52 p.
, ECS Transactions, ISSN 1938-5862 ; 50
Elevated temperature, Epitaxial regrowth, Fabrication process, High saturation current, On-wafer measurements, Power Integrations, Room temperature, Vertical channels
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-144799DOI: 10.1149/05003.0045ecstISI: 000337755900005ScopusID: 2-s2.0-84885781942ISBN: 978-160768351-3OAI: oai:DiVA.org:kth-144799DiVA: diva2:714835
2nd Symposium on Gallium Nitride (GaN) and Silicon Carbide (SiC) Power Technologies - ECS Fall 2012 Meeting; Honolulu, HI; United States; 7 October 2012 through 12 October 2012
QC 201404292014-04-292014-04-292015-10-06Bibliographically approved