Mobility enhancement by integration of TmSiO IL in 0.65nm EOT high-k/metal gate MOSFETs
2013 (English)In: 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC), IEEE Computer Society, 2013, 155-158 p.Conference paper (Refereed)
Thulium silicate has been demonstrated as a possible replacement of chemical oxide interfacial layers for extended scalability of high-k/metal gate MOSFETs. In this work, thulium silicate was integrated in a scaled HfO 2/TiN gate-last CMOS process, achieving an EOT of 0.65 nm and well-behaved and reproducible IV and CV characteristics with almost symmetric threshold voltages, low subthreshold slope and low hysteresis. Comparison with reference devices employing chemical oxide interfacial layers shows improvement in terms of leakage current density and electron and hole mobility. Specifically, channel mobility is enhanced by 20% in N-MOSFETs and by 15% in P-MOSFETs at an inversion charge density of 1013cm-2, yielding values of 180 and 75 cm2/Vs at EOT = 0.65 and 0.8 nm respectively.
Place, publisher, year, edition, pages
IEEE Computer Society, 2013. 155-158 p.
, European Solid State Device Research Conference. Proceedings, ISSN 1930-8876
CMOS integrated circuits, Hafnium oxides, Silicates, Thulium, C-V characteristic, Channel mobility, High-k/metal gates, Interfacial layer, Inversion charge density, Mobility enhancement, Reference devices, Subthreshold slope
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-145113DOI: 10.1109/ESSDERC.2013.6818842ISI: 000342231600036ScopusID: 2-s2.0-84902181747ISBN: 978-147990649-9OAI: oai:DiVA.org:kth-145113DiVA: diva2:716172
43rd European Solid-State Device Research Conference, ESSDERC 2013; Bucharest; Romania; 16 September 2013 through 20 September 2013
QC 201409112014-05-082014-05-082014-10-27Bibliographically approved