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A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
KTH, School of Computer Science and Communication (CSC), Computational Biology, CB.ORCID iD: 0000-0002-2358-7815
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2014 (English)In: 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE , 2014, 578-585 p.Conference paper, Published paper (Refereed)
Abstract [en]

A multi-chip custom digital super-computer called eBrain for simulating Bayesian Confidence Propagation Neural Network (BCPNN) model of the human brain has been proposed. It uses Hybrid Memory Cube (HMC), the 3D stacked DRAM memories for storing synaptic weights that are integrated with a custom designed logic chip that implements the BCPNN model. In 22nm node, eBrain executes BCPNN in real time with 740 TFlops/s while accessing 30 TBs synaptic weights with a bandwidth of 112 TBs/s while consuming less than 6 kWs power for the typical case. This efficiency is three orders better than general purpose supercomputers in the same technology node.

Place, publisher, year, edition, pages
IEEE , 2014. 578-585 p.
Series
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Keyword [en]
3d-stacked drams, Human brain, Hybrid memory, Logic chips, Neural network model, Simulation machine, Synaptic weight, Technology nodes
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-145446DOI: 10.1109/ASPDAC.2014.6742953ISI: 000350791700104Scopus ID: 2-s2.0-84897883326ISBN: 978-147992816-3 (print)OAI: oai:DiVA.org:kth-145446DiVA: diva2:718809
Conference
2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014; Suntec; Singapore; 20 January 2014 through 23 January 2014
Note

QC 20140522

Available from: 2014-05-22 Created: 2014-05-21 Last updated: 2016-04-28Bibliographically approved
In thesis
1. SiLago: Enabling System Level Automation Methodology to Design Custom High-Performance Computing Platforms: Toward Next Generation Hardware Synthesis Methodologies
Open this publication in new window or tab >>SiLago: Enabling System Level Automation Methodology to Design Custom High-Performance Computing Platforms: Toward Next Generation Hardware Synthesis Methodologies
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Place, publisher, year, edition, pages
Stockholm, Sweden: KTH Royal Institute of Technology, 2016. 56 p.
Series
TRITA-ICT, 2016:05
Keyword
System Level Synthesis, High Level Synthesis, VLSI Design Methodology, Brain-like Computation, Neuromorphic Hardware, Address Generation, Thread Level Parallelism
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-185787 (URN)978-91-7595-900-9 (ISBN)
Public defence
2016-05-17, Sal B, Electrum 229, Isafjordsgatan 22, Kista, Stockholm, 20:24 (English)
Opponent
Supervisors
Note

QC 20160428

Available from: 2016-04-28 Created: 2016-04-27 Last updated: 2016-04-28Bibliographically approved

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Hemani, Ahmed

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
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Language
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  • en-GB
  • en-US
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Output format
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