Fabrication of strained Ge on insulator via room temperature wafer bonding
2014 (English)In: 2014 15th International Conference on Ultimate Integration on Silicon, ULIS 2014, IEEE Computer Society, 2014, 81-84 p.Conference paper (Refereed)
This work describes a strained germanium on insulator (GeOI) fabrication process using wafer bonding and etch-back techniques. The strained Ge layer is fabricated epitaxially using reduced pressure chemical vapor deposition (RPCVD). The strained Ge is grown pseudomorphic on top of a partially relaxed Si 0.66Ge0.34 layer. Wafer bonding is performed at room temperature without post-anneal processes and the etch-back steps are performed without mechanical grinding and chemical mechanical polishing (CMP).
Place, publisher, year, edition, pages
IEEE Computer Society, 2014. 81-84 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-146687DOI: 10.1109/ULIS.2014.6813911ISI: 000341731300021ScopusID: 2-s2.0-84901380569ISBN: 978-1-4799-3718-9OAI: oai:DiVA.org:kth-146687DiVA: diva2:725331
2014 15th International Conference on Ultimate Integration on Silicon, ULIS 2014; Stockholm; Sweden; 7 April 2014 through 9 April 2014
QC 201406162014-06-162014-06-132014-10-09Bibliographically approved