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Implementation and evaluation of configuration scrubbing on CGRAs: A case study
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
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2013 (English)In: 2013 International Symposium on System-on-Chip, SoC 2013 - Proceedings, IEEE Computer Society, 2013, 6675262- p.Conference paper (Refereed)
Abstract [en]

This paper investigates the overhead imposed by various configuration scrubbing techniques used in fault-tolerant Coarse Grained Reconfigurable Arrays (CGRAs). Today, reconfigurable architectures host large configuration memories. As we progress further in the nanometer regime, these configuration memories have become increasingly susceptible to single event upsets caused e.g. by cosmic radiation. Configuration scrubbing is a frequently used technique to protect these configuration memories against single event upsets. Existing works on configuration scrubbing deal only with FPGA without any reference to the CGRAs (in which configuration memories consume up to 50% of silicon area). Moreover, in the known literature lacks a comprehensive comparison of various configuration scrubbing techniques to guide system designers about the merits/demerits of different scrubbing methods which could be applied to CGRAs. To address these problems, in this paper we classify various configuration scrubbing techniques and quantify their trade-offs when implemented on a CGRA. Synthesis results reveal that scrubbing logic incurs negligible silicon overhead (up to 3% of the area of computational units). Simulation results obtained for a few algorithms/applications (FFT, FIR, matrix multiplication, and WLAN) show that the choice of the configuration scrubbing scheme (external vs. internal) has significant impact on both the size of configuration memory and the number of reconfiguration cycles (respectively 20-80% more and up to 38 times more for the former).

Place, publisher, year, edition, pages
IEEE Computer Society, 2013. 6675262- p.
Keyword [en]
Application specific integrated circuits, Electric network analysis, Field programmable gate arrays (FPGA), Programmable logic controllers, Radiation hardening, Reconfigurable architectures, Silicon, Coarse-grained reconfigurable arrays, Comprehensive comparisons, Computational units, Configuration memory, MAtrix multiplication, Reconfiguration cycles, Scrubbing techniques, Single event upsets, Computer control systems
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-146935DOI: 10.1109/ISSoC.2013.6675262ISI: 000335010100007ScopusID: 2-s2.0-84896997064OAI: diva2:727207
2013 15th International Symposium on System-on-Chip, SoC 2013; Tampere; Finland; 23 October 2013 through 24 October 2013

QC 20140619

Available from: 2014-06-19 Created: 2014-06-18 Last updated: 2014-06-19Bibliographically approved

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Jafri, SyedHemani, AhmedTenhunen, Hannu
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