Efficient distributed memory management in a multi-core H.264 decoder on FPGA
2013 (English)In: 2013 International Symposium on System-on-Chip, SoC 2013 - Proceedings, IEEE Computer Society, 2013, 6675256- p.Conference paper (Refereed)
Memory management is a challenging issue of multicore architecture. With growing core numbers, Distributed Shared Memory (DSM) is becoming a general trend. In this paper, a DSM based multi-core architecture is explored and evaluated via an H.264 decoder application. The memory access and communication over Network-on-Chips is managed by the Data Management Engine (DME). Experimental results realized on an Altera Strati x VI show that 9-node distributed memory system increases performance by 1.5x compared to centralized memory. Moreover, the performance of proposed DSM architecture grows linearly with the number of cores deployed.
Place, publisher, year, edition, pages
IEEE Computer Society, 2013. 6675256- p.
DME, DSM, FPGA, H.264 decoder, Multi-core
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-146940DOI: 10.1109/ISSoC.2013.6675256ISI: 000335010100001ScopusID: 2-s2.0-84896988445OAI: oai:DiVA.org:kth-146940DiVA: diva2:729111
2013 15th International Symposium on System-on-Chip, SoC 2013; Tampere; Finland; 23 October 2013 through 24 October 2013
QC 201406252014-06-252014-06-182014-06-25Bibliographically approved