Asynchronous BFT for low power networks on chip
2010 (English)In: ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, IEEE , 2010, 3240-3243 p.Conference paper (Refereed)
Asynchronous Butterfly Fat Tree (BFT) architecture is proposed to achieve low power Network on Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches (αdata satisfies a certain condition. The area of Asynchronous BFT switch is increased by 25% as compared to Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by up to 33% as compared to the power dissipation of the conventional Synchronous architecture when the αdata equals 0.2 and the activity factor of the control signals is equal to 1/64 of the αdata. The total metal resources required to implement Asynchronous design is decreased by 12%.
Place, publisher, year, edition, pages
IEEE , 2010. 3240-3243 p.
, IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
BFT, GALS, Low power, NoC
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-149605DOI: 10.1109/ISCAS.2010.5537922ISI: 000287216003114ScopusID: 2-s2.0-77956006799ISBN: 978-1-4244-5309-2OAI: oai:DiVA.org:kth-149605DiVA: diva2:740451
2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, 30 May 2010 through 2 June 2010, Paris, France
QC 201408252014-08-252014-08-252014-08-25Bibliographically approved