Distributed DVFS using rationally-related frequencies and discrete voltage levels
2010 (English)In: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design, IEEE , 2010, 247-252 p.Conference paper (Refereed)
We have defined a flexible latency-insensitive design style called Globally Ratiochronous Locally Synchronous (GRLS), based on quantized voltage levels and rationally-related clock frequencies. In this paper we present the infrastructure necessary to enable Distributed DVFS in such a system and analyze its overheads, quantitatively showing how, with minimal overheads, we obtain energy benefits that are close to those of a totally ideal GALS approach. The benefits that we show, coupled with the complexity and performance benefits of GRLS, which we briefly analyze, show how this approach is a strong competitor to GALS.
Place, publisher, year, edition, pages
IEEE , 2010. 247-252 p.
, Proceedings of the International Symposium on Low Power Electronics and Design, ISSN 1533-4678
Design, Clock frequency, Discrete voltage, Energy benefits, Latency-insensitive designs, Performance benefits, Voltage levels, Power electronics
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-149725DOI: 10.1145/1840845.1840897ScopusID: 2-s2.0-77957948826ISBN: 978-145030146-6OAI: oai:DiVA.org:kth-149725DiVA: diva2:741784
16th ACM/IEEE International Symposium on Low-Power Electronics and Design, ISLPED'10, 18 August 2010 through 20 August 2010, Austin, TX, United States
QC 201408292014-08-292014-08-262014-08-29Bibliographically approved