A low-power, medium-resolution, high-speed CMOS pipelined ADC
2010 (English)In: 28th Norchip Conference, NORCHIP 2010, 2010, 5669438- p.Conference paper (Refereed)
This paper presents the systematic design approach of a low-power, medium-resolution, high-speed pipelined Analog-to-Digital Converter (ADC). The ADC is implemented in 180nm digital CMOS technology. The converter achieves signal-to-noise distortion ratio of 59.8 dB, spurious-free dynamic range of 89 dB and effective number of bits of 9.64-bits at sampling speed of 50MHz with an input signal frequency of 4MHz. The peak differential-nonlinearity of the converter is 0.28/-0.17LSB and integral-nonlinearity of the converter is +0.42/-0.41LSB. The proposed 10-bit, 50MS/sec pipelined ADC consumes 24.5mW amount of power from 1.8V supply.
Place, publisher, year, edition, pages
2010. 5669438- p.
Analog-to-digital sub converter (ADSC), Dynamic range (DR), Multiplying digital-to-analog converter (MDAC), Operational transconductance amplifier (OTA), Signal-to-noise distortion ratio (SNDR), Spurious free dynamic range (SFDR)
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-150081DOI: 10.1109/NORCHIP.2010.5669438ScopusID: 2-s2.0-78751514577ISBN: 978-142448973-2OAI: oai:DiVA.org:kth-150081DiVA: diva2:741921
28th Norchip Conference, NORCHIP 2010, 15 November 2010 through 16 November 2010, Tampere, Finland
QC 201408292014-08-292014-08-292014-08-29Bibliographically approved