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Integration of metallic source/drain (MSD) contacts in nanoscaled CMOS technology
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0002-5845-3032
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-6705-1660
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2010 (English)In: ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2010, 41-45 p.Conference paper, Published paper (Refereed)
Abstract [en]

An overview of metallic source/drain (MSD) contacts in nanoscaled MOSFET technology is provided in this paper. MSD contacts offer several benefits for nanoscaled CMOS, i.e., extremely low S/D parasitic resistance, abruptly sharp junctions between S/D and channel and preferably low temperature processing. In order to achieve high performance MSD MOSFETs, many design parameters such as Schottky barrier height (SBH), S/D to gate underlap, top Si layer thickness, oxide thickness and so on should be optimized. Recently, a lot of efforts have been invested in MSD MOSFETs based on Pt- and Ni-silicide implementation and several promising results have been reported in literature. The experimental work as well as the results of Monte Carlo simulations by this research team and by other research teams is discussed in this paper. It will be shown that the present results place MSD MOSFETs as a competitive candidate for future generations of CMOS technology.

Place, publisher, year, edition, pages
2010. 41-45 p.
Keyword [en]
CMOS technology, Design parameters, Experimental works, Future generations, Gate underlap, Low temperature processing, Monte Carlo Simulation, MOS-FET, MOSFETs, Nanoscaled, Ni-silicide, Oxide thickness, Parasitic resistances, Research teams, Schottky barrier heights, Si layer
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-150072DOI: 10.1109/ICSICT.2010.5667860Scopus ID: 2-s2.0-78751499473ISBN: 978-142445798-4 (print)OAI: oai:DiVA.org:kth-150072DiVA: diva2:741958
Conference
2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, 1 November 2010 through 4 November 2010, Shanghai, China
Note

QC 20140829

Available from: 2014-08-29 Created: 2014-08-29 Last updated: 2014-08-29Bibliographically approved

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Hellström, Per ErikMalm, Bengt Gunnar

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