An improved hardware implementation of the Grain stream cipher
2010 (English)In: Proceedings - 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2010, 2010, 433-440 p.Conference paper (Refereed)
A common approach to protect confidential information is to use a stream cipher which combines plain text bits with a pseudo-random bit sequence. Among the existing stream ciphers, Non-Linear Feedback Shift Register (NLFSR)-based ones provide the best trade-off between cryptographic security and hardware efficiency. In this paper, we show how to further improve the hardware efficiency of the Grain stream cipher. By transforming the NLFSR of Grain from its original Fibonacci configuration to the Galois configuration and by introducing new hardware solutions, we double the throughput of the 80 and 128-bit key 1 bit/cycle architectures of Grain with no area and power penalty.
Place, publisher, year, edition, pages
2010. 433-440 p.
Confidential information, Cryptographic security, Fibonacci, Hardware efficiency, Hardware implementations, Hardware solutions, Non-linear, Plain text, Power penalty, Pseudo random bit sequences, Stream Ciphers, Architecture, Cryptography, Hardware, Hydraulics, Shift registers, Systems analysis, Computer hardware description languages
Computer Systems Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-150068DOI: 10.1109/DSD.2010.49ScopusID: 2-s2.0-78649872685ISBN: 978-076954171-6OAI: oai:DiVA.org:kth-150068DiVA: diva2:741985
13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2010, 1 September 2010 through 3 September 2010, Lille, France
QC 201408292014-08-292014-08-292014-08-29Bibliographically approved