A 1-cycle 2 GHz bufferless router for network-on-chip
2011 (English)In: Guofang Keji Daxue Xuebao/Journal of National University of Defense Technology, ISSN 1001-2486, Vol. 33, no 6, 42-47 p.Article in journal (Refereed) Published
Recently, bufferless router, which does not need buffers, has become a low-cost solution for Network-on-Chip. To improve the performance of the bufferless router, a 1-cycle high-performance bufferless router was proposed for Network-on-Chip. The router used a simple permutation network instead of the serialized switch allocator and the crossbar to achieve high performance. Compared with the virtual channel router and the baseline bufferless router, the proposed bufferless router can achieve the frequency of 2 GHz with small area cost under TSMC 65 nm technology. Simulation results under both synthetic and application workloads demonstrate that the proposed bufferless router achieves much less average packet latency than the virtual channel router and other bufferless routers.
Place, publisher, year, edition, pages
2011. Vol. 33, no 6, 42-47 p.
Bufferless router, Deflection routing, Network-on-chip, Permutation network, Allocators, Low-cost solution, Network on chip, Packet latencies, Small area, Virtual channels, Servers, Switching circuits, VLSI circuits, Routers
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-149768ScopusID: 2-s2.0-84863072483OAI: oai:DiVA.org:kth-149768DiVA: diva2:743067
QC 201409032014-09-032014-08-272014-09-03Bibliographically approved