Power analysis for Asynchronous CLICH Network-on-Chip
2010 (English)In: Proceedings - IEEE International SOC Conference, SOCC 2010, IEEE , 2010, 499-504 p.Conference paper (Refereed)
Asynchronous Chip-Level Integration of Communicating Heterogeneous Elements (CLICH) architecture is proposed to achieve low power Network-on-Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches ( data satisfies a certain condition. The area of Asynchronous CLICH switch is increased by 25% as compared to the Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by 21% as compared to the power dissipation in the conventional Synchronous architecture when the ( data equals 0.2 and the activity factor of the control signals is equal to 1 over 64 of the ( data. The total metal resources required to implement Asynchronous design is decreased by 7%.
Place, publisher, year, edition, pages
IEEE , 2010. 499-504 p.
CLICH, GALS, Low Power, NoC
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-150243DOI: 10.1109/SOCC.2010.5784677ScopusID: 2-s2.0-79960727490ISBN: 978-142446683-2OAI: oai:DiVA.org:kth-150243DiVA: diva2:743136
23rd IEEE International SOC Conference, SOCC 2010; Las Vegas, NV; United States; 27 September 2010 through 29 September 2010;
QC 201409032014-09-032014-09-012014-09-03Bibliographically approved