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Highly reliable and power efficient NOC interconnects
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT. (RaMSiS Group)
2011 (English)In: NORCHIP, 2011Conference paper (Refereed)
Abstract [en]

Network on chip (NOC) architecture interconnects consume significant amount of power, have a large propagation delay and are susceptible to error due to deep sub-micron (DSM) noise. Major challenge that NOC design expected to face is related to intrinsic reliability. By incorporating error control coding schemes along the NOC interconnects, NOC architectures are able to provide correct functionality in the presence of different transient noise source. In this paper we present a novel coding scheme that increase the reliability of the NOC where the area is reduced by 19% and the consumed power by NOC interconnects is decreased by 51%. Butterfly fat tree architecture consumes the minimum power as compared to other NOC architectures.

Place, publisher, year, edition, pages
, 2011 NORCHIP
Keyword [en]
Error Control Coding, Interconnects, Network on Chip, Power Efficient, Reliable, Coding scheme, Deep sub-micron, Network-on-chip architectures, NoC architectures, NoC design, Propagation delays, Transient noise, Optical interconnects, Codes (symbols)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-149891DOI: 10.1109/NORCHP.2011.6126732ScopusID: 2-s2.0-84856885737ISBN: 9781457705168OAI: diva2:743464
2011 NORCHIP, 14 November 2011 through 15 November 2011, Lund

QC 20140904

Available from: 2014-09-04 Created: 2014-08-28 Last updated: 2014-09-04Bibliographically approved

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Ismail, Muhammad
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