A NoC system generator for the Sea-of-Cores era
2011 (English)In: 8th FPGAworld Conference - Academic Proceedings 2011, 2011, 35-40 p.Conference paper (Refereed)
Multi-core systems are getting bigger. The number of cores is doubling every 18 months, in corollary with the reformulated Moore's law. Soon, the number of cores that can be integrated together in a system will be so large, that it is appropriate to talk about a new SoC design paradigm, the Sea-of-Cores era. This development will not end, even when CMOS cannot be made any smaller. Instead, with the development of Through-Silicon Vias (TSVs), chips will be stacked in 3D, promising continuous scaling for a very long time ahead. As systems grow, programming and debugging of them will become harder. Methods for generating the systems from higher-level specifications will be necessary to manage design complexity. Also, there will be so many processors to be programmed, that the SW also will have to be automatically generated and distributed, much in the same way as a synthesis and place & route tool is doing today for HW. In this paper, we present a NoC generator that can generate an arbitrarily large Multi-core platform from an XML configuration file, targeted for single-chip FPGA platforms. The NoC generator also generates a device driver prototype together with a small test program that can be used as a template for creating larger programs.
Place, publisher, year, edition, pages
2011. 35-40 p.
FPGA, hardware platform, MPI, MPSoC, multi-core, NoC, Multi core, Field programmable gate arrays (FPGA), Microprocessor chips, Program debugging
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-149890DOI: 10.1145/2157871.2157875ScopusID: 2-s2.0-84858730194ISBN: 9781450310215OAI: oai:DiVA.org:kth-149890DiVA: diva2:743473
FPGAWorld-2011, Proceedings of the 8th FPGAWorld Conference, Stockholm, 2011, available through ACM DL
QC 201409042014-09-042014-08-282016-04-08Bibliographically approved