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Error analysis of integrated resistor attenuation network
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2010 (English)In: Proceedings - International Conference on Electrical and Control Engineering, ICECE 2010, 2010, 3714-3717 p.Conference paper, Published paper (Refereed)
Abstract [en]

The model and synthesis method of integrated linear attenuation network (LAC) used in mixed signal SoC for digital instrument are addressed in this paper. The model and synthesis method of the LAC used for electronics instrument is related with the application and implementation method. To the signal generator used in some electronics instrument, the LAC architecture could be linear and synthesized by resistor network and some additional circuits. Therefore, the spectrum properties of the LAC are relayed on the spectrum properties of additional circuits. The synthesis method is derived the formula of the LAC model. With the model, the integrated resistor network in the LAC used for measurement circuit module could be reduced. The LAC architecture synthesis method is suitable for the application of implementing a LAC with integrated circuit technology.

Place, publisher, year, edition, pages
2010. 3714-3717 p.
Keyword [en]
Embedded technology, Instrument, SoC
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-150021DOI: 10.1109/iCECE.2010.906Scopus ID: 2-s2.0-79952223358ISBN: 978-076954031-3 (print)OAI: oai:DiVA.org:kth-150021DiVA: diva2:743616
Conference
International Conference on Electrical and Control Engineering, ICECE 2010, 26 June 2010 through 28 June 2010, Wuhan, China
Note

QC 20140904

Available from: 2014-09-04 Created: 2014-08-29 Last updated: 2014-09-04Bibliographically approved

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Li, Shuo

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Citation style
  • apa
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  • ieee
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  • vancouver
  • Other style
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Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf